From: lkcl <lkcl@web>
Date: Fri, 27 Apr 2018 04:25:56 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~5439
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1c9ff5c5face02c914fe0d405619f52f2bd17fa4;p=libreriscv.git

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diff --git a/harmonised_rvv_rvp/discussion.mdwn b/harmonised_rvv_rvp/discussion.mdwn
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+# Comments
+
+## enabling/disabling individual 8 and 16-bit operations in SIMD blocks
+
+* At the end of a loop, how are the three end operations of 4-wide 8-bit operations to be disabled (to avoid "SIMD considered harmful"?)
+* Likewise at the beginning of a loop, how are (up to) the first three operations to be disabled?
+* Likewise the last (and first) of 2-wide 16-bit operations?
+* What about predication within a 4-wide 8-bit group?
+* Likewise what about predication within a 2-wide 16-bit group?