From: Cesar Strauss <cestrauss@gmail.com>
Date: Sun, 21 Feb 2021 17:18:15 +0000 (-0300)
Subject: Hide the register augmentation traces by default
X-Git-Tag: convert-csv-opcode-to-binary~175
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1ca8487e48fd656699e07070b86fb53d6de76480;p=soc.git

Hide the register augmentation traces by default

This saves some vertical space if you are not interested in seeing this
level of detail, but it is still there if you need it.
Needs the latest nmutil version for it to work.
---

diff --git a/src/soc/simple/test/test_runner.py b/src/soc/simple/test/test_runner.py
index 60f049ee..381395fa 100644
--- a/src/soc/simple/test/test_runner.py
+++ b/src/soc/simple/test/test_runner.py
@@ -313,7 +313,8 @@ class TestRunner(FHDLTestCase):
 
         styles = {
             'dec': {'base': 'dec'},
-            'bin': {'base': 'bin'}
+            'bin': {'base': 'bin'},
+            'closed': {'closed': True}
         }
 
         traces = [
@@ -327,7 +328,7 @@ class TestRunner(FHDLTestCase):
             {'comment': 'svp64 decoding'},
             'svp64_rm[23:0]',
             ('dec2.extra[8:0]', 'bin'),
-            ('register augmentation', 'dec', [
+            ('register augmentation', 'dec', 'closed', [
                 {'comment': 'v3.0b registers'},
                 'dec2.dec_o.RT[4:0]',
                 'dec2.dec_a.RA[4:0]',