From: Jackson Woodruff <jackson.woodruff@arm.com>
Date: Wed, 13 Sep 2017 14:08:49 +0000 (+0000)
Subject: [Aarch64, Patch] Update failing testcase pr62178.c
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1cb656f82c5d03ce40495bbe59111ac3cc26b713;p=gcc.git

[Aarch64, Patch] Update failing testcase pr62178.c

This patch changes pr62178.c so that it now scans
for two `ldr`s, one into an `s` register, instead
of a `ld1r` as before. Also add a scan for an mla
instruction.

The `ld1r` was needed when this should have generated
a mla by vector. Now that we can generate an mla by
element instruction and can load directly into the
simd register, it is cheaper to not do the ld1r
which needlessly duplicates the single element used
across the whole vector register.

Committed on behalf of Jackson Woodruff

gcc/testsuite/

	* gcc.target/aarch64/pr62178.c: Updated testcase
	to scan for two ldrs and an mla.

From-SVN: r252086
---

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 55a9720825f..4b57651e24c 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2017-09-13  Jackson Woodruff  <jackson.woodruff@arm.com>
+
+	* gcc.target/aarch64/pr62178.c: Updated testcase
+	to scan for two ldrs and an mla.
+
 2017-09-13  Paolo Carlini  <paolo.carlini@oracle.com>
 
 	PR c++/59949
diff --git a/gcc/testsuite/gcc.target/aarch64/pr62178.c b/gcc/testsuite/gcc.target/aarch64/pr62178.c
index b80ce686560..1bf6d838d3a 100644
--- a/gcc/testsuite/gcc.target/aarch64/pr62178.c
+++ b/gcc/testsuite/gcc.target/aarch64/pr62178.c
@@ -14,4 +14,6 @@ void foo (void) {
     }
 }
 
-/* { dg-final { scan-assembler "ld1r\\t\{v\[0-9\]+\."} } */
+/* { dg-final { scan-assembler "ldr\\ts\[0-9\]+, \\\[x\[0-9\]+, \[0-9\]+\\\]!" } } */
+/* { dg-final { scan-assembler "ldr\\tq\[0-9\]+, \\\[x\[0-9\]+\\\], \[0-9\]+" } } */
+/* { dg-final { scan-assembler "mla\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.s\\\[0\\\]" } } */