From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 18 Apr 2022 07:10:28 +0000 (+0200)
Subject: verific: allow memories to be inferred in loops (vhdl)
X-Git-Tag: yosys-0.17~26
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1cc281ca6fc4035a8f48fd7b7a0289cb580c3f4c;p=yosys.git

verific: allow memories to be inferred in loops (vhdl)
---

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index b53bad7da..284d5db31 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -2553,6 +2553,7 @@ struct VerificPass : public Pass {
 #ifdef VERIFIC_VHDL_SUPPORT
 			RuntimeFlags::SetVar("vhdl_extract_dualport_rams", 0);
 			RuntimeFlags::SetVar("vhdl_extract_multiport_rams", 1);
+			RuntimeFlags::SetVar("vhdl_allow_any_ram_in_loop", 1);
 
 			RuntimeFlags::SetVar("vhdl_support_variable_slice", 1);
 			RuntimeFlags::SetVar("vhdl_ignore_assertion_statements", 0);