From: Andrew Zonenberg <azonenberg@drawersteak.com>
Date: Wed, 19 Oct 2016 03:46:49 +0000 (-0700)
Subject: Fixed typo in last commit
X-Git-Tag: yosys-0.7~15^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1cca1563c64cd521a384a5df404dbccb3e06cb5c;p=yosys.git

Fixed typo in last commit
---

diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v
index 76bf058d2..80746be0f 100644
--- a/techlibs/greenpak4/cells_sim.v
+++ b/techlibs/greenpak4/cells_sim.v
@@ -308,7 +308,7 @@ endmodule
 module GP_PGEN(input wire nRST, input wire CLK, output reg OUT);
 	initial OUT = 0;
 	parameter PATTERN_DATA = 16'h0;
-	parameter PATTERN_LEN = 4'd16;
+	parameter PATTERN_LEN = 5'd16;
 
 	reg[3:0] count = 0;
 	always @(posedge CLK) begin