From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 21 Aug 2020 12:06:03 +0000 (+0100)
Subject: first test of down-converted load/store from 64 to 32 bit
X-Git-Tag: semi_working_ecp5~280
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1cce9a0d566f33b96b0303d133d42778cf1bdcdf;p=soc.git

first test of down-converted load/store from 64 to 32 bit
---

diff --git a/src/soc/bus/test/test_minerva.py b/src/soc/bus/test/test_minerva.py
index d70655ff..5d784b1f 100644
--- a/src/soc/bus/test/test_minerva.py
+++ b/src/soc/bus/test/test_minerva.py
@@ -12,7 +12,7 @@ class TestSRAMBareLoadStoreUnit(BareLoadStoreUnit):
                 isinstance(pspec.dmem_test_depth, int)):
             depth = pspec.dmem_test_depth
         else:
-            depth = 32
+            depth = 64
         print("TestSRAMBareLoadStoreUnit depth", depth)
 
         self.mem = Memory(width=self.data_wid, depth=depth)