From: lkcl <lkcl@web>
Date: Fri, 14 Apr 2023 20:15:25 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls008_v1~10
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1cd875cc9451b9f3b7683b9c823721e04dcd4f64;p=libreriscv.git

---

diff --git a/openpower/sv/svstep.mdwn b/openpower/sv/svstep.mdwn
index e9864cdf1..980771e75 100644
--- a/openpower/sv/svstep.mdwn
+++ b/openpower/sv/svstep.mdwn
@@ -65,7 +65,7 @@ As a 32-bit instruction, `svstep` may be itself be Vector-Prefixed, as
 as it will in Vertical-First Mode.
 
 Example: to obtain the full set of possible computed element
-indices use `sv.svstep RT.v,SVI,1` which will store all computed element
+indices use `sv.svstep *RT,SVi,1` which will store all computed element
 indices, starting from RT.  If Rc=1 then a co-result Vector of CR Fields
 will also be returned, comprising the "loop end-points" of each of the inner
 loops when either Matrix Mode or DCT/FFT is set.  In other words,