From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 16 Jun 2019 11:51:48 +0000 (+0100)
Subject: make overflow roundz a property (Overflow no longer a module)
X-Git-Tag: ls180-24jan2020~985
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1ce0996c90fe2c2134c97e5cae44c89c66ecd6c5;p=ieee754fpu.git

make overflow roundz a property (Overflow no longer a module)
---

diff --git a/src/ieee754/fpadd/add1.py b/src/ieee754/fpadd/add1.py
index 12054312..408b6075 100644
--- a/src/ieee754/fpadd/add1.py
+++ b/src/ieee754/fpadd/add1.py
@@ -35,7 +35,7 @@ class FPAddStage1Mod(FPState, Elaboratable):
         """ links module to inputs and outputs
         """
         m.submodules.add1 = self
-        m.submodules.add1_out_overflow = self.o.of
+        #m.submodules.add1_out_overflow = self.o.of
 
         m.d.comb += self.i.eq(i)
 
diff --git a/src/ieee754/fpcommon/fpbase.py b/src/ieee754/fpcommon/fpbase.py
index b62a1153..6f14f5b1 100644
--- a/src/ieee754/fpcommon/fpbase.py
+++ b/src/ieee754/fpcommon/fpbase.py
@@ -569,7 +569,7 @@ class Overflow: #(Elaboratable):
         self.sticky = Signal(reset_less=True)    # tot[0]
         self.m0 = Signal(reset_less=True)        # mantissa zero bit
 
-        self.roundz = Signal(reset_less=True)
+        #self.roundz = Signal(reset_less=True)
 
     def __iter__(self):
         yield self.guard
@@ -583,11 +583,9 @@ class Overflow: #(Elaboratable):
                 self.sticky.eq(inp.sticky),
                 self.m0.eq(inp.m0)]
 
-    def elaborate(self, platform):
-        m = Module()
-        m.d.comb += self.roundz.eq(self.guard & \
-                                   (self.round_bit | self.sticky | self.m0))
-        return m
+    @property
+    def roundz(self):
+        return self.guard & (self.round_bit | self.sticky | self.m0)
 
 
 class FPBase:
diff --git a/src/ieee754/fpcommon/postnormalise.py b/src/ieee754/fpcommon/postnormalise.py
index c45bf1e9..1d9ee94f 100644
--- a/src/ieee754/fpcommon/postnormalise.py
+++ b/src/ieee754/fpcommon/postnormalise.py
@@ -61,13 +61,13 @@ class FPNorm1ModSingle(Elaboratable):
         m.d.comb += self.o.roundz.eq(of.roundz)
 
         #m.submodules.norm1_out_z = self.o.z
-        m.submodules.norm1_out_overflow = of
+        #m.submodules.norm1_out_overflow = of
         #m.submodules.norm1_in_z = self.i.z
-        m.submodules.norm1_in_overflow = self.i.of
+        #m.submodules.norm1_in_overflow = self.i.of
 
         i = self.ispec()
         m.submodules.norm1_insel_z = insel_z = FPNumBase(i.z)
-        m.submodules.norm1_insel_overflow = i.of
+        #m.submodules.norm1_insel_overflow = i.of
 
         espec = (len(insel_z.e), True)
         ediff_n126 = Signal(espec, reset_less=True)