From: Sebastien Bourdeauducq Date: Thu, 22 Dec 2011 23:36:07 +0000 (+0100) Subject: example: flow conversion X-Git-Tag: 24jan2021_ls180~2099^2~1108 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1ce4fbdb98842a44a4805802661fe031c4f64bba;p=litex.git example: flow conversion --- diff --git a/examples/dataflow.py b/examples/dataflow.py new file mode 100644 index 00000000..31aed2e1 --- /dev/null +++ b/examples/dataflow.py @@ -0,0 +1,6 @@ +from migen.fhdl import verilog +from migen.flow.ala import * + +act = Divider(32) +frag = act.get_control_fragment() + act.get_process_fragment() +print(verilog.Convert(frag))