From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 23 May 2020 03:13:22 +0000 (+0100)
Subject: select bits 2:5 from BC to get CR0 to 7 in DecodeCRin
X-Git-Tag: div_pipeline~922
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1cfd61edb85672dddfaf9c41f6874514dc2073d9;p=soc.git

select bits 2:5 from BC to get CR0 to 7 in DecodeCRin
---

diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index dbd87f96..e5aa0321 100644
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -310,7 +310,7 @@ class DecodeCRIn(Elaboratable):
                 comb += self.cr_bitfield_o.data.eq(self.dec.BT[2:5])
                 comb += self.cr_bitfield_o.ok.eq(1)
             with m.Case(CRInSel.BC):
-                comb += self.cr_bitfield.data.eq(self.dec.BC[0:-1])
+                comb += self.cr_bitfield.data.eq(self.dec.BC[2:5])
                 comb += self.cr_bitfield.ok.eq(1)
             with m.Case(CRInSel.WHOLE_REG):
                 comb += self.whole_reg.eq(1)