From: Luke Kenneth Casson Leighton Date: Wed, 1 Jul 2020 16:40:14 +0000 (+0100) Subject: bit 58 not bit 88 X-Git-Tag: convert-csv-opcode-to-binary~2393 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1d09d2455985e602a5799e1fafac5cea6b1cb72d;p=libreriscv.git bit 58 not bit 88 --- diff --git a/openpower/isa/system.mdwn b/openpower/isa/system.mdwn index a640ea375..12cbf47ab 100644 --- a/openpower/isa/system.mdwn +++ b/openpower/isa/system.mdwn @@ -79,7 +79,7 @@ Pseudo-code: if (MSR[29:31] != 0b010) | (SRR1[29:31] != 0b000) then MSR[29:31] <- SRR1[29:31] MSR[48] <- SRR1[48] | SRR1[49] - MSR[58] <- SRR1[88] | SRR1[49] + MSR[58] <- SRR1[58] | SRR1[49] MSR[59] <- SRR1[59] | SRR1[49] MSR[0:2] <- SRR1[0:2] MSR[4:28] <- SRR1[4:28] @@ -105,7 +105,7 @@ Pseudo-code: if (MSR[29:31] != 0b010) | (HSRR1[29:31] != 0b000) then MSR[29:31] <- HSRR1[29:31] MSR[48] <- HSRR1[48] | HSRR1[49] - MSR[58] <- HSRR1[88] | HSRR1[49] + MSR[58] <- HSRR1[58] | HSRR1[49] MSR[59] <- HSRR1[59] | HSRR1[49] MSR[0:28] <- HSRR1[0:28] MSR[32] <- HSRR1[32]