From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 23 Dec 2019 22:40:59 +0000 (-0800)
Subject: Fix OPMODE for PCIN->PCOUT cascades in xc6s, check B[01]REG too
X-Git-Tag: working-ls180~902^2~2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1d0ac659ad37af7fa3d32a95bf04c4ce0e009792;p=yosys.git

Fix OPMODE for PCIN->PCOUT cascades in xc6s, check B[01]REG too
---

diff --git a/passes/pmgen/xilinx_dsp_cascade.pmg b/passes/pmgen/xilinx_dsp_cascade.pmg
index 9fdefff31..b4c2b348f 100644
--- a/passes/pmgen/xilinx_dsp_cascade.pmg
+++ b/passes/pmgen/xilinx_dsp_cascade.pmg
@@ -99,14 +99,21 @@ finally
 					add_siguser(cascade, dsp);
 
 					SigSpec opmode = port(dsp_pcin, \OPMODE, Const(0, 7));
-					if (P == 17)
-						opmode[6] = State::S1;
-					else if (P == 0)
-						opmode[6] = State::S0;
-					else log_abort();
+					if (dsp->type.in(\DSP48A, \DSP48A1)) {
+						log_assert(P == 0);
+						opmode[3] = State::S0;
+						opmode[2] = State::S1;
+					}
+					else if (dsp->type.in(\DSP48E1)) {
+						if (P == 17)
+							opmode[6] = State::S1;
+						else if (P == 0)
+							opmode[6] = State::S0;
+						else log_abort();
 
-					opmode[5] = State::S0;
-					opmode[4] = State::S1;
+						opmode[5] = State::S0;
+						opmode[4] = State::S1;
+					}
 					dsp_pcin->setPort(\OPMODE, opmode);
 
 					log_debug("PCOUT -> PCIN cascade for %s -> %s\n", log_id(dsp), log_id(dsp_pcin));
@@ -307,8 +314,11 @@ code argQ clock BREG
 						goto reject_BREG;
 					if (dffcemux && port(dffcemux, \S) != port(prev, CEB, State::S0))
 						goto reject_BREG;
-					if (dffD == unextend(port(prev, \B)))
+					if (dffD == unextend(port(prev, \B))) {
+						if (next->type.in(\DSP48A, \DSP48A1) && param(prev, \B0REG, 0) != 0)
+							goto reject_BREG;
 						BREG = 1;
+					}
 				}
 			}
 		}