From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 27 Jun 2019 02:17:11 +0000 (-0700)
Subject: Add write_xaiger into CHANGELOG
X-Git-Tag: working-ls180~1237^2~28
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1d0be89214466aa5120d6fc0e155c6366ae8e802;p=yosys.git

Add write_xaiger into CHANGELOG
---

diff --git a/CHANGELOG b/CHANGELOG
index f0154a81e..73115600c 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -22,6 +22,7 @@ Yosys 0.8 .. Yosys 0.8-dev
     - Added "muxcover -dmux=<cost>"
     - Added "muxcover -nopartial"
     - Added "muxpack" pass
+    - Added "write_xaiger" backend
     - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
     - Added "synth_xilinx -abc9" (experimental)
     - Added "synth_ice40 -abc9" (experimental)