From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 26 Oct 2018 08:43:02 +0000 (+0100)
Subject: mention variable register file length
X-Git-Tag: convert-csv-opcode-to-binary~4892
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1d152926ee9f72e1b546a008005cceb012ed4cb5;p=libreriscv.git

mention variable register file length
---

diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn
index edd50ed2f..f8ed0cabe 100644
--- a/simple_v_extension/specification.mdwn
+++ b/simple_v_extension/specification.mdwn
@@ -1659,3 +1659,9 @@ answer: they're not vectorised, so not a problem
 
 TODO: update elwidth to be default / 8 / 16 / 32
 
+---
+
+TODO: document different lengths for INT / FP regfiles, and provide
+as part of info register. 00=32, 01=64, 10=128, 11=reserved.
+
+