From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 8 Feb 2017 09:40:33 +0000 (+0100)
Subject: Add PSL parser mode to verific front-end
X-Git-Tag: yosys-0.8~513
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1d1f56a3617dcee6d856a29d1d8576969bf8dce5;p=yosys.git

Add PSL parser mode to verific front-end
---

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index f5efdea7e..f3b997dc5 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -888,12 +888,12 @@ struct VerificPass : public Pass {
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
-		log("    verific {-vlog95|-vlog2k|-sv2005|-sv2009|-sv} <verilog-file>..\n");
+		log("    verific {-vlog95|-vlog2k|-sv2005|-sv2009|-sv|-vlpsl} <verilog-file>..\n");
 		log("\n");
 		log("Load the specified Verilog/SystemVerilog files into Verific.\n");
 		log("\n");
 		log("\n");
-		log("    verific {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008} <vhdl-file>..\n");
+		log("    verific {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdpsl} <vhdl-file>..\n");
 		log("\n");
 		log("Load the specified VHDL files into Verific.\n");
 		log("\n");
@@ -950,6 +950,13 @@ struct VerificPass : public Pass {
 			return;
 		}
 
+		if (args.size() > 1 && args[1] == "-vlpsl") {
+			for (size_t argidx = 2; argidx < args.size(); argidx++)
+				if (!veri_file::Analyze(args[argidx].c_str(), veri_file::VERILOG_PSL))
+					log_cmd_error("Reading `%s' in VERILOG_PSL mode failed.\n", args[argidx].c_str());
+			return;
+		}
+
 		if (args.size() > 1 && args[1] == "-vhdl87") {
 			vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1987").c_str());
 			for (size_t argidx = 2; argidx < args.size(); argidx++)
@@ -982,6 +989,14 @@ struct VerificPass : public Pass {
 			return;
 		}
 
+		if (args.size() > 1 && args[1] == "-vhdpsl") {
+			vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_2008").c_str());
+			for (size_t argidx = 2; argidx < args.size(); argidx++)
+				if (!vhdl_file::Analyze(args[argidx].c_str(), "work", vhdl_file::VHDL_PSL))
+					log_cmd_error("Reading `%s' in VHDL_PSL mode failed.\n", args[argidx].c_str());
+			return;
+		}
+
 		if (args.size() > 1 && args[1] == "-import")
 		{
 			std::set<Netlist*> nl_todo, nl_done;