From: Sebastien Bourdeauducq Date: Wed, 10 Jul 2013 17:11:02 +0000 (+0200) Subject: examples/sim/abstract_transactions_lasmi: check data X-Git-Tag: 24jan2021_ls180~2099^2~531 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1d33c61308df220d57387b87a1581d27a058ca9a;p=litex.git examples/sim/abstract_transactions_lasmi: check data --- diff --git a/examples/sim/abstract_transactions_lasmi.py b/examples/sim/abstract_transactions_lasmi.py index 258470bc..e53ca7ca 100644 --- a/examples/sim/abstract_transactions_lasmi.py +++ b/examples/sim/abstract_transactions_lasmi.py @@ -4,27 +4,32 @@ from migen.bus import lasmibus from migen.sim.generic import Simulator def my_generator(n): + bank = n % 4 for x in range(4): - t = TWrite(4*n+x, 0x100+x) + t = TWrite(4*bank+x, 0x1000*bank + 0x100*x) yield t - print("Wrote in {0} cycle(s)".format(t.latency)) + print("{0}: Wrote in {1} cycle(s)".format(n, t.latency)) for x in range(4): - t = TRead(4*n+x) + t = TRead(4*bank+x) yield t - print("Read {0:x} in {1:x} cycle(s)".format(t.data, t.latency)) + print("{0}: Read {1:x} in {2} cycle(s)".format(n, t.data, t.latency)) + assert(t.data == 0x1000*bank + 0x100*x) class MyModel(lasmibus.TargetModel): def read(self, bank, address): - #print("read from bank {0} address {1}".format(bank, address)) - return 0x1000*bank + 0x200+address + r = 0x1000*bank + 0x100*address + #print("read from bank {0} address {1} -> {2:x}".format(bank, address, r)) + return r def write(self, bank, address, data, we): print("write to bank {0} address {1:x} data {2:x}".format(bank, address, data)) + assert(data == 0x1000*bank + 0x100*address) class TB(Module): def __init__(self): - self.submodules.controller = lasmibus.Target(MyModel(), aw=4, dw=32, nbanks=4, read_latency=4, write_latency=1) + self.submodules.controller = lasmibus.Target(MyModel(), aw=4, dw=32, nbanks=4, req_queue_size=4, + read_latency=4, write_latency=1) self.submodules.xbar = lasmibus.Crossbar([self.controller.bus], 4, 2) self.initiators = [lasmibus.Initiator(my_generator(n), bus) for n, bus in enumerate(self.xbar.masters)] self.submodules += self.initiators