From: Cesar Strauss <cestrauss@gmail.com>
Date: Thu, 24 Sep 2020 16:27:53 +0000 (-0300)
Subject: Fix whitespace, remove unused imports
X-Git-Tag: 24jan2021_ls180~333
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1d36d034a4e0bd2dfe1c3eb672ff41e88a841cdc;p=soc.git

Fix whitespace, remove unused imports
---

diff --git a/src/soc/experiment/alu_fsm.py b/src/soc/experiment/alu_fsm.py
index 51f04950..46593dd1 100644
--- a/src/soc/experiment/alu_fsm.py
+++ b/src/soc/experiment/alu_fsm.py
@@ -19,16 +19,14 @@ The basic rules are:
 from nmigen import Elaboratable, Signal, Module, Cat
 from nmigen.cli import rtlil
 from math import log2
-import os
 
 from nmutil.iocontrol import PrevControl, NextControl
 
 from soc.fu.base_input_record import CompOpSubsetBase
-from soc.decoder.power_enums import (MicrOp, Function)
 
 from nmutil.gtkw import write_gtkw
 from nmutil.sim_tmp_alternative import (Simulator, is_engine_pysim,
-                                         nmigen_sim_top_module)
+                                        nmigen_sim_top_module)
 
 
 class CompFSMOpSubset(CompOpSubsetBase):
@@ -39,7 +37,6 @@ class CompFSMOpSubset(CompOpSubsetBase):
         super().__init__(layout, name=name)
 
 
-
 class Dummy:
     pass
 
@@ -65,7 +62,7 @@ class Shifter(Elaboratable):
         def __init__(self, width):
             self.data = Signal(width, name="p_data_i")
             self.shift = Signal(width, name="p_shift_i")
-            self.ctx = Dummy() # comply with CompALU API
+            self.ctx = Dummy()  # comply with CompALU API
 
         def _get_data(self):
             return [self.data, self.shift]