From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 15 Mar 2020 22:16:20 +0000 (+0000)
Subject: crossreference to bugreport
X-Git-Tag: div_pipeline~1698
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1d3f6f57b204964df567c333906d2e6512ab5a77;p=soc.git

crossreference to bugreport
---

diff --git a/src/soc/scoreboard/addr_match.py b/src/soc/scoreboard/addr_match.py
index 4d38089b..d32aa98b 100644
--- a/src/soc/scoreboard/addr_match.py
+++ b/src/soc/scoreboard/addr_match.py
@@ -1,5 +1,8 @@
 """ Load / Store partial address matcher
 
+Related bugreports:
+* http://bugs.libre-riscv.org/show_bug.cgi?id=216
+
 Loads and Stores do not need a full match (CAM), they need "good enough"
 avoidance.  Around 11 bits on a 64-bit address is "good enough".