From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 19 Feb 2020 18:45:10 +0000 (-0800)
Subject: clean: ignore specify-s inside cells when determining whether to keep
X-Git-Tag: working-ls180~790^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1d401a7991f4c0f133b7355acc400132da1aa4a0;p=yosys.git

clean: ignore specify-s inside cells when determining whether to keep
---

diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index 2f69b3d4c..f5bb40050 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -51,20 +51,26 @@ struct keep_cache_t
 		if (cache.count(module))
 			return cache.at(module);
 
-		cache[module] = true;
-		if (!module->get_bool_attribute(ID::keep)) {
-			bool found_keep = false;
+		bool found_keep = false;
+		if (module->get_bool_attribute(ID::keep))
+			found_keep = true;
+		else
 			for (auto cell : module->cells())
-				if (query(cell)) found_keep = true;
-			cache[module] = found_keep;
-		}
+				if (query(cell, true /* ignore_specify */)) {
+					found_keep = true;
+					break;
+				}
+		cache[module] = found_keep;
 
-		return cache[module];
+		return found_keep;
 	}
 
-	bool query(Cell *cell)
+	bool query(Cell *cell, bool ignore_specify = false)
 	{
-		if (cell->type.in(ID($memwr), ID($meminit), ID($assert), ID($assume), ID($live), ID($fair), ID($cover), ID($specify2), ID($specify3), ID($specrule)))
+		if (cell->type.in(ID($memwr), ID($meminit), ID($assert), ID($assume), ID($live), ID($fair), ID($cover)))
+			return true;
+
+		if (!ignore_specify && cell->type.in(ID($specify2), ID($specify3), ID($specrule)))
 			return true;
 
 		if (cell->has_keep_attr())
diff --git a/tests/various/specify.ys b/tests/various/specify.ys
index a2b6038e4..9d55b8eb5 100644
--- a/tests/various/specify.ys
+++ b/tests/various/specify.ys
@@ -55,4 +55,23 @@ equiv_induct -seq 5
 equiv_status -assert
 design -reset
 
-read_verilog specify.v
+read_verilog -specify <<EOT
+(* blackbox *)
+module test7_sub(input i, output o);
+specify
+    (i => o) = 1;
+endspecify
+assign o = ~i;
+endmodule
+
+module test7(input i, output o);
+    wire w;
+    test7_sub unused(i, w);
+    test7_sub used(i, o);
+endmodule
+EOT
+hierarchy
+cd test7
+clean
+select -assert-count 1 c:used
+select -assert-none c:* c:used %d