From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 21 May 2020 19:35:33 +0000 (+0100)
Subject: move Logical over to use CompLogicalOpSubset
X-Git-Tag: div_pipeline~967
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1d4827cbc08b754acb25dc3a4bceca2728fc242a;p=soc.git

move Logical over to use CompLogicalOpSubset
---

diff --git a/src/soc/fu/logical/pipe_data.py b/src/soc/fu/logical/pipe_data.py
index 27e2a694..332fd60e 100644
--- a/src/soc/fu/logical/pipe_data.py
+++ b/src/soc/fu/logical/pipe_data.py
@@ -2,7 +2,7 @@ from nmigen import Signal, Const
 from ieee754.fpcommon.getop import FPPipeContext
 from soc.fu.pipe_data import IntegerData
 from soc.fu.alu.pipe_data import ALUOutputData, CommonPipeSpec
-from soc.fu.alu.alu_input_record import CompALUOpSubset # TODO: replace
+from soc.fu.logical.logical_input_record import CompLogicalOpSubset
 
 
 class LogicalInputData(IntegerData):
@@ -31,7 +31,6 @@ class LogicalInputData(IntegerData):
                       self.xer_so.eq(i.xer_so)]
 
 
-# TODO: replace CompALUOpSubset with CompLogicalOpSubset
 class LogicalPipeSpec(CommonPipeSpec):
     regspec = (LogicalInputData.regspec, ALUOutputData.regspec)
-    opsubsetkls = CompALUOpSubset
+    opsubsetkls = CompLogicalOpSubset