From: Zachary Snow <zach@zachjs.com>
Date: Sun, 7 Feb 2021 04:54:17 +0000 (-0500)
Subject: verlog: allow shadowing module ports within generate blocks
X-Git-Tag: working-ls180~87^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1d5f3fe5064146955dafdabafe7180ff79c95d08;p=yosys.git

verlog: allow shadowing module ports within generate blocks

This is a somewhat obscure edge case I encountered while working on test
cases for earlier changes. Declarations in generate blocks should not be
checked against the list of ports. This change also adds a check
forbidding declarations within generate blocks being tagged as inputs or
outputs.
---

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index fb5846f7b..0aae25353 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -1784,7 +1784,13 @@ wire_name:
 			}
 			rewriteAsMemoryNode(node, $2);
 		}
-		if (current_function_or_task == NULL) {
+		if (current_function_or_task) {
+			if (node->is_input || node->is_output)
+				node->port_id = current_function_or_task_port_id++;
+		} else if (ast_stack.back()->type == AST_GENBLOCK) {
+			if (node->is_input || node->is_output)
+				frontend_verilog_yyerror("Cannot declare module port `%s' within a generate block.", $1->c_str());
+		} else {
 			if (do_not_require_port_stubs && (node->is_input || node->is_output) && port_stubs.count(*$1) == 0) {
 				port_stubs[*$1] = ++port_counter;
 			}
@@ -1799,9 +1805,6 @@ wire_name:
 				if (node->is_input || node->is_output)
 					frontend_verilog_yyerror("Module port `%s' is not declared in module header.", $1->c_str());
 			}
-		} else {
-			if (node->is_input || node->is_output)
-				node->port_id = current_function_or_task_port_id++;
 		}
 		//FIXME: for some reason, TOK_ID has a location which always points to one column *after* the real last column...
 		SET_AST_NODE_LOC(node, @1, @1);
diff --git a/tests/simple/genblk_port_shadow.v b/tests/simple/genblk_port_shadow.v
new file mode 100644
index 000000000..a04631a20
--- /dev/null
+++ b/tests/simple/genblk_port_shadow.v
@@ -0,0 +1,10 @@
+module top(x);
+	generate
+		if (1) begin : blk
+			wire x;
+			assign x = 0;
+		end
+	endgenerate
+	output wire x;
+	assign x = blk.x;
+endmodule
diff --git a/tests/verilog/genblk_port_decl.ys b/tests/verilog/genblk_port_decl.ys
new file mode 100644
index 000000000..589d3d2e1
--- /dev/null
+++ b/tests/verilog/genblk_port_decl.ys
@@ -0,0 +1,12 @@
+logger -expect error "Cannot declare module port `\\x' within a generate block\." 1
+read_verilog <<EOT
+module top(x);
+    generate
+        if (1) begin : blk
+            output wire x;
+            assign x = 1;
+        end
+    endgenerate
+    output wire x;
+endmodule
+EOT