From: lkcl Date: Thu, 9 Sep 2021 11:52:11 +0000 (+0100) Subject: (no commit message) X-Git-Tag: DRAFT_SVP64_0_1~171 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1d638685ada6f97c2e21253e1ef6903699237fdb;p=libreriscv.git --- diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn index 4c1363652..cbd3edfe7 100644 --- a/openpower/sv/cr_ops.mdwn +++ b/openpower/sv/cr_ops.mdwn @@ -69,14 +69,13 @@ The principle of data-dependent fail-first is that if a Condition Test fails then VL (Vector Length) is truncated at that point. In the case of Arithmetic SVP64 Operations the Condition Register Field generated from Rc=1 is used, however with CR-based operations that CR result is provided -by the operation itself. In some cases however, CR-based operations -operate on entire CR fields, not just one bit. +by the operation itself. Data-dependent SVP64 Vectorised Operations involving the creation or modification of a CR can require an extra two bits, which are not available -in the compact space of the `MODE` Field. With the concept of element +in the compact space of the SVP64 RM `MODE` Field. With the concept of element width overrides being meaningless for CR Fields it is possible to use the -`ELWIDTH` field for extra fields. +`ELWIDTH` field for alternative purposes. Condition Register based operations such as `sv.mfcr` and `sv.crand` can thus be made more flexible. However the rules that apply in this section