From: Ahmed Irfan Date: Tue, 11 Feb 2014 12:28:05 +0000 (+0100) Subject: register output corrected X-Git-Tag: yosys-0.2.0~18^2^2~2 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1d64b3e0084814774cb2a0eb5a9c99dbe1101bc2;p=yosys.git register output corrected --- diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc index 2c8546f05..03ef183a5 100644 --- a/backends/btor/btor.cc +++ b/backends/btor/btor.cc @@ -647,7 +647,7 @@ struct BtorDumper log(" - width is %d\n", output_width); int cond = dump_sigspec(&cell->connections.at(RTLIL::IdString("\\CLK")), 1); bool polarity = cell->parameters.at(RTLIL::IdString("\\CLK_POLARITY")).as_bool(); - const RTLIL::SigSpec* cell_output = &cell->connections.at(RTLIL::IdString("\\D")); + const RTLIL::SigSpec* cell_output = &cell->connections.at(RTLIL::IdString("\\Q")); int value = dump_sigspec(&cell->connections.at(RTLIL::IdString("\\D")), output_width); unsigned start_bit = 0; for(unsigned i=0; ichunks.size(); ++i)