From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 13 Apr 2021 13:50:45 +0000 (+0000)
Subject: whoops forgot settings.py
X-Git-Tag: LS180_RC3~120
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1d74a0c55f712b496166cf81f86e48e7d640bce5;p=soclayout.git

whoops forgot settings.py
---

diff --git a/experiments10_verilog/coriolis2/settings.py b/experiments10_verilog/coriolis2/settings.py
index 807fae0..e4e3362 100644
--- a/experiments10_verilog/coriolis2/settings.py
+++ b/experiments10_verilog/coriolis2/settings.py
@@ -54,7 +54,6 @@ with overlay.CfgCache(priority=Cfg.Parameter.Priority.UserFile) as cfg:
     cfg.etesian.aspectRatio = 1.0
     cfg.anabatic.edgeLenght = 24
     cfg.anabatic.edgeWidth = 8
-    cfg.anabatic.routingGauge = 'FlexLib'
     cfg.anabatic.topRoutingLayer = 'METAL5'
     cfg.katana.eventsLimit = 4000000
     cfg.etesian.effort = 2
diff --git a/experiments10_verilog/freepdk_c4m45/coriolis2/settings.py b/experiments10_verilog/freepdk_c4m45/coriolis2/settings.py
new file mode 100644
index 0000000..cc10a52
--- /dev/null
+++ b/experiments10_verilog/freepdk_c4m45/coriolis2/settings.py
@@ -0,0 +1,44 @@
+# -*- Mode:Python -*-
+
+import os
+import socket
+import helpers
+
+NdaDirectory = None
+if os.environ.has_key('NDA_TOP'):
+    NdaDirectory = os.environ['NDA_TOP']
+if not NdaDirectory:
+    hostname = socket.gethostname()
+    if hostname.startswith('lepka'):
+        NdaDirectory = '/dsk/l1/jpc/crypted/soc/techno'
+        if not os.path.isdir(NdaDirectory):
+            print '[ERROR] You forgot to mount the NDA encrypted directory, stupid!'
+    else:
+        NdaDirectory = '/users/soft/techno/techno'
+helpers.setNdaTopDir( NdaDirectory )
+
+import Cfg
+from   CRL     import AllianceFramework
+from   helpers import overlay, l, u, n
+from   NDA.node45.freepdk45_c4m import techno, FlexLib, LibreSOCIO
+
+techno.setup()
+FlexLib.setup()
+LibreSOCIO.setup()
+
+with overlay.CfgCache(priority=Cfg.Parameter.Priority.UserFile) as cfg:
+    cfg.misc.catchCore           = False
+    cfg.misc.minTraceLevel       = 12300
+    cfg.misc.maxTraceLevel       = 12400
+    cfg.misc.info                = False
+    cfg.misc.paranoid            = False
+    cfg.misc.bug                 = False
+    cfg.misc.logMode             = True
+    cfg.misc.verboseLevel1       = True
+    cfg.misc.verboseLevel2       = True
+    cfg.etesian.graphics         = 3
+    cfg.etesian.spaceMargin      = 0.10
+    cfg.katana.eventsLimit       = 4000000
+    af  = AllianceFramework.get()
+    env = af.getEnvironment()
+    env.setCLOCK( '^sys_clk$|^ck|^jtag_tck$' )
diff --git a/experiments10_verilog/freepdk_c4m45/doDesign.py b/experiments10_verilog/freepdk_c4m45/doDesign.py
index 3de3798..2628842 100644
--- a/experiments10_verilog/freepdk_c4m45/doDesign.py
+++ b/experiments10_verilog/freepdk_c4m45/doDesign.py
@@ -31,8 +31,8 @@ def scriptMain ( **kw ):
     """The mandatory function to be called by Coriolis CGT/Unicorn."""
     global af
     rvalue = True
-    coreSize   = u(3*90.0)
-    chipBorder = u(4*214.0 + 10*13.0)
+    coreSize   = u(3.5*90.0)
+    chipBorder = u(4.5*214.0 + 10*13.0)
     try:
         helpers.setTraceLevel( 550 )
         cell, editor = plugins.kwParseMain( **kw )
@@ -76,6 +76,7 @@ def scriptMain ( **kw ):
         adderConf.cfg.etesian.spaceMargin = 0.05
         adderConf.cfg.anabatic.searchHalo = 2
         adderConf.cfg.anabatic.globalIterations = 20
+        adderConf.cfg.anabatic.routingGauge = 'FlexLib'
         adderConf.cfg.anabatic.topRoutingLayer = 'METAL5'
         adderConf.cfg.block.spareSide = u(7*13)
         #adderConf.cfg.chip.padCoreSide = 'North'