From: lkcl <lkcl@web>
Date: Tue, 19 Apr 2022 13:00:00 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2701
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1d79d1b8c6e263e004a5caff2368e6d19a50566b;p=libreriscv.git

---

diff --git a/openpower/sv/biginteger.mdwn b/openpower/sv/biginteger.mdwn
index d88c2b132..638eecd92 100644
--- a/openpower/sv/biginteger.mdwn
+++ b/openpower/sv/biginteger.mdwn
@@ -19,4 +19,14 @@ Dynamic SIMD ALUs for maximum performance and effectiveness.
 # Add and Subtract
 
 Surprisingly, no new additional instructions are required to perform
-a straightforward big-integer add or subtract.  Vectorised `addex`
+a straightforward big-integer add or subtract.  Vectorised `addeo`
+or `addex` is perfectly sufficient to produce arbitrary-length
+big-integer add due to the rules set in SVP64 that all Vector Operations
+are directly equivalent to the strict Program Order Execution of
+their element-level operations.
+
+Thus, due to sequential execution of `addeo` both consuming and producing
+a CA Flag, `sv.addeo` is in effect an alias for Vectorised add.  As such,
+implementors are entirely at liberty to recognise Horizontal-First Vector
+adds and send the vector of registers to a much larger and wider back-end
+ALU.