From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 6 Dec 2006 10:56:34 +0000 (-0500)
Subject: Make syscalls flatten their register indices, and also call into the ISA's setSyscall... 
X-Git-Tag: m5_2.0_beta3~274^2~29
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1d7d7df315e3bd9ddb3eedfed7f612e83778c252;p=gem5.git

Make syscalls flatten their register indices, and also call into the ISA's setSyscallReturn function rather than having a duplicated one.

--HG--
extra : convert_revision : 1e83ef629a7fd143f2e35e68abaa56f81d6b9d9e
---

diff --git a/src/cpu/o3/sparc/cpu_impl.hh b/src/cpu/o3/sparc/cpu_impl.hh
index 536a620bf..f92d863cc 100644
--- a/src/cpu/o3/sparc/cpu_impl.hh
+++ b/src/cpu/o3/sparc/cpu_impl.hh
@@ -285,35 +285,24 @@ template <class Impl>
 TheISA::IntReg
 SparcO3CPU<Impl>::getSyscallArg(int i, int tid)
 {
-    return this->readArchIntReg(SparcISA::ArgumentReg0 + i, tid);
+    IntReg idx = TheISA::flattenIntIndex(this->tcBase(tid),
+            SparcISA::ArgumentReg0 + i);
+    return this->readArchIntReg(idx, tid);
 }
 
 template <class Impl>
 void
 SparcO3CPU<Impl>::setSyscallArg(int i, IntReg val, int tid)
 {
-    this->setArchIntReg(SparcISA::ArgumentReg0 + i, val, tid);
+    IntReg idx = TheISA::flattenIntIndex(this->tcBase(tid),
+            SparcISA::ArgumentReg0 + i);
+    this->setArchIntReg(idx, val, tid);
 }
 
 template <class Impl>
 void
 SparcO3CPU<Impl>::setSyscallReturn(SyscallReturn return_value, int tid)
 {
-    // check for error condition.  SPARC syscall convention is to
-    // indicate success/failure in reg the carry bit of the ccr
-    // and put the return value itself in the standard return value reg ().
-    if (return_value.successful()) {
-        // no error, clear XCC.C
-        this->setMiscReg(SparcISA::MISCREG_CCR,
-                this->readMiscReg(SparcISA::MISCREG_CCR, tid) & 0xEE, tid);
-        this->setArchIntReg(SparcISA::ReturnValueReg,
-                return_value.value(), tid);
-    } else {
-        // got an error, set XCC.C
-        this->setMiscReg(SparcISA::MISCREG_CCR,
-                this->readMiscReg(SparcISA::MISCREG_CCR, tid) | 0x11, tid);
-        this->setArchIntReg(SparcISA::ReturnValueReg,
-                return_value.value(), tid);
-    }
+    TheISA::setSyscallReturn(return_value, this->tcBase(tid));
 }
 #endif