From: Luke Kenneth Casson Leighton Date: Wed, 24 Nov 2021 12:31:52 +0000 (+0000) Subject: whoops merged the two write-ports for RT and RA-with-update X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1d89c8e51b2fd021757a102c88f6da60357d6f5e;p=soc.git whoops merged the two write-ports for RT and RA-with-update --- diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py index ade46baf..7d98bb9b 100644 --- a/src/soc/simple/core.py +++ b/src/soc/simple/core.py @@ -776,7 +776,7 @@ class NonProductionCore(ControlBase): name = "%s_%s_%s_%d" % (funame, regfile, regname, idx) # get (or set up) a write-latched copy of write register number write = Signal.like(_write, name="write_"+name) - rname = "%s_%s_%s" % (funame, regfile, regname) + rname = "%s_%s_%s_%d" % (funame, regfile, regname, idx) if rname not in fu.wr_latches: wrl = Signal.like(_write, name="wrlatch_"+rname) fu.wr_latches[rname] = write