From: whitequark Date: Fri, 11 Oct 2019 11:47:42 +0000 (+0000) Subject: Consistently use {!r}, not '{!r}' in diagnostics. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1d8a397404025329e4bbe44d1e2bdf8e4f6b548a;p=nmigen.git Consistently use {!r}, not '{!r}' in diagnostics. This can cause confusion: * If the erroneous object is None, it is printed as 'None', which appears as a string (and could be the result of converting None to a string.) * If the erroneous object is a string, it is printed as '''', which is a rather strange combination of quotes. --- diff --git a/nmigen/back/pysim.py b/nmigen/back/pysim.py index 0949d5e..ceb9409 100644 --- a/nmigen/back/pysim.py +++ b/nmigen/back/pysim.py @@ -420,7 +420,7 @@ class Simulator: if inspect.isgeneratorfunction(process): process = process() if not (inspect.isgenerator(process) or inspect.iscoroutine(process)): - raise TypeError("Cannot add a process '{!r}' because it is not a generator or " + raise TypeError("Cannot add a process {!r} because it is not a generator or " "a generator function" .format(process)) return process @@ -744,12 +744,12 @@ class Simulator: lhs_signals = cmd.lhs._lhs_signals() for signal in lhs_signals: if not signal in self._signals: - raise ValueError("Process '{}' sent a request to set signal '{!r}', " + raise ValueError("Process '{}' sent a request to set signal {!r}, " "which is not a part of simulation" .format(self._name_process(process), signal)) signal_slot = self._signal_slots[signal] if self._comb_signals[signal_slot]: - raise ValueError("Process '{}' sent a request to set signal '{!r}', " + raise ValueError("Process '{}' sent a request to set signal {!r}, " "which is a part of combinatorial assignment in " "simulation" .format(self._name_process(process), signal)) @@ -780,7 +780,7 @@ class Simulator: continue else: - raise TypeError("Received unsupported command '{!r}' from process '{}'" + raise TypeError("Received unsupported command {!r} from process '{}'" .format(cmd, self._name_process(process))) cmd = process.send(None) diff --git a/nmigen/hdl/ast.py b/nmigen/hdl/ast.py index f142c1d..f4528ed 100644 --- a/nmigen/hdl/ast.py +++ b/nmigen/hdl/ast.py @@ -396,7 +396,7 @@ class Const(Value): shape = shape, self.value < 0 self.width, self.signed = shape if not isinstance(self.width, int) or self.width < 0: - raise TypeError("Width must be a non-negative integer, not '{!r}'" + raise TypeError("Width must be a non-negative integer, not {!r}" .format(self.width)) self.value = self.normalize(self.value, shape) @@ -429,7 +429,7 @@ class AnyValue(Value, DUID): shape = shape, False self.width, self.signed = shape if not isinstance(self.width, int) or self.width < 0: - raise TypeError("Width must be a non-negative integer, not '{!r}'" + raise TypeError("Width must be a non-negative integer, not {!r}" .format(self.width)) def shape(self): @@ -559,9 +559,9 @@ def Mux(sel, val1, val0): class Slice(Value): def __init__(self, value, start, end, *, src_loc_at=0): if not isinstance(start, int): - raise TypeError("Slice start must be an integer, not '{!r}'".format(start)) + raise TypeError("Slice start must be an integer, not {!r}".format(start)) if not isinstance(end, int): - raise TypeError("Slice end must be an integer, not '{!r}'".format(end)) + raise TypeError("Slice end must be an integer, not {!r}".format(end)) n = len(value) if start not in range(-(n+1), n+1): @@ -597,9 +597,9 @@ class Slice(Value): class Part(Value): def __init__(self, value, offset, width, stride=1, *, src_loc_at=0): if not isinstance(width, int) or width < 0: - raise TypeError("Part width must be a non-negative integer, not '{!r}'".format(width)) + raise TypeError("Part width must be a non-negative integer, not {!r}".format(width)) if not isinstance(stride, int) or stride <= 0: - raise TypeError("Part stride must be a positive integer, not '{!r}'".format(stride)) + raise TypeError("Part stride must be a positive integer, not {!r}".format(stride)) super().__init__(src_loc_at=src_loc_at) self.value = value @@ -693,7 +693,7 @@ class Repl(Value): """ def __init__(self, value, count, *, src_loc_at=0): if not isinstance(count, int) or count < 0: - raise TypeError("Replication count must be a non-negative integer, not '{!r}'" + raise TypeError("Replication count must be a non-negative integer, not {!r}" .format(count)) super().__init__(src_loc_at=src_loc_at) @@ -770,7 +770,7 @@ class Signal(Value, DUID): DeprecationWarning, stacklevel=2 + src_loc_at) if name is not None and not isinstance(name, str): - raise TypeError("Name must be a string, not '{!r}'".format(name)) + raise TypeError("Name must be a string, not {!r}".format(name)) self.name = name or tracer.get_var_name(depth=2 + src_loc_at, default="$signal") if shape is None: @@ -798,7 +798,7 @@ class Signal(Value, DUID): self.width, self.signed = shape if not isinstance(self.width, int) or self.width < 0: - raise TypeError("Width must be a non-negative integer, not '{!r}'".format(self.width)) + raise TypeError("Width must be a non-negative integer, not {!r}".format(self.width)) reset_width = bits_for(reset, self.signed) if reset != 0 and reset_width > self.width: @@ -913,7 +913,7 @@ class ClockSignal(Value): def __init__(self, domain="sync", *, src_loc_at=0): super().__init__(src_loc_at=src_loc_at) if not isinstance(domain, str): - raise TypeError("Clock domain name must be a string, not '{!r}'".format(domain)) + raise TypeError("Clock domain name must be a string, not {!r}".format(domain)) if domain == "comb": raise ValueError("Domain '{}' does not have a clock".format(domain)) self.domain = domain @@ -949,7 +949,7 @@ class ResetSignal(Value): def __init__(self, domain="sync", allow_reset_less=False, *, src_loc_at=0): super().__init__(src_loc_at=src_loc_at) if not isinstance(domain, str): - raise TypeError("Clock domain name must be a string, not '{!r}'".format(domain)) + raise TypeError("Clock domain name must be a string, not {!r}".format(domain)) if domain == "comb": raise ValueError("Domain '{}' does not have a reset".format(domain)) self.domain = domain @@ -1221,7 +1221,7 @@ class Statement: if isinstance(obj, Statement): return _StatementList([obj]) else: - raise TypeError("Object '{!r}' is not an nMigen statement".format(obj)) + raise TypeError("Object {!r} is not an nMigen statement".format(obj)) @final @@ -1311,7 +1311,7 @@ class Switch(Statement): elif isinstance(key, Enum): key = format(key.value, "b").rjust(len(self.test), "0") else: - raise TypeError("Object '{!r}' cannot be used as a switch key" + raise TypeError("Object {!r} cannot be used as a switch key" .format(key)) assert len(key) == len(self.test) new_keys = (*new_keys, key) @@ -1500,7 +1500,7 @@ class ValueKey: elif isinstance(self.value, Initial): self._hash = 0 else: # :nocov: - raise TypeError("Object '{!r}' cannot be used as a key in value collections" + raise TypeError("Object {!r} cannot be used as a key in value collections" .format(self.value)) def __hash__(self): @@ -1548,7 +1548,7 @@ class ValueKey: elif isinstance(self.value, Initial): return True else: # :nocov: - raise TypeError("Object '{!r}' cannot be used as a key in value collections" + raise TypeError("Object {!r} cannot be used as a key in value collections" .format(self.value)) def __lt__(self, other): @@ -1566,7 +1566,7 @@ class ValueKey: self.value.start < other.value.start and self.value.end < other.value.end) else: # :nocov: - raise TypeError("Object '{!r}' cannot be used as a key in value collections") + raise TypeError("Object {!r} cannot be used as a key in value collections") def __repr__(self): return "<{}.ValueKey {!r}>".format(__name__, self.value) @@ -1592,7 +1592,7 @@ class SignalKey: elif type(signal) is ResetSignal: self._intern = (2, signal.domain) else: - raise TypeError("Object '{!r}' is not an nMigen signal".format(signal)) + raise TypeError("Object {!r} is not an nMigen signal".format(signal)) def __hash__(self): return hash(self._intern) @@ -1604,7 +1604,7 @@ class SignalKey: def __lt__(self, other): if type(other) is not SignalKey: - raise TypeError("Object '{!r}' cannot be compared to a SignalKey".format(signal)) + raise TypeError("Object {!r} cannot be compared to a SignalKey".format(signal)) return self._intern < other._intern def __repr__(self): diff --git a/nmigen/hdl/dsl.py b/nmigen/hdl/dsl.py index 830aaa0..6a14edf 100644 --- a/nmigen/hdl/dsl.py +++ b/nmigen/hdl/dsl.py @@ -454,7 +454,7 @@ class Module(_ModuleBuilderRoot, Elaboratable): def _add_submodule(self, submodule, name=None): if not hasattr(submodule, "elaborate"): - raise TypeError("Trying to add '{!r}', which does not implement .elaborate(), as " + raise TypeError("Trying to add {!r}, which does not implement .elaborate(), as " "a submodule".format(submodule)) if name == None: self._anon_submodules.append(submodule) diff --git a/nmigen/hdl/ir.py b/nmigen/hdl/ir.py index 7ff40d0..de65d31 100644 --- a/nmigen/hdl/ir.py +++ b/nmigen/hdl/ir.py @@ -70,7 +70,7 @@ class Fragment: code = obj.elaborate.__code__ obj = obj.elaborate(platform) else: - raise AttributeError("Object '{!r}' cannot be elaborated".format(obj)) + raise AttributeError("Object {!r} cannot be elaborated".format(obj)) if obj is None and code is not None: warnings.warn_explicit( message=".elaborate() returned None; missing return statement?", diff --git a/nmigen/hdl/mem.py b/nmigen/hdl/mem.py index 38ec383..1101dab 100644 --- a/nmigen/hdl/mem.py +++ b/nmigen/hdl/mem.py @@ -11,10 +11,10 @@ __all__ = ["Memory", "ReadPort", "WritePort", "DummyPort"] class Memory: def __init__(self, *, width, depth, init=None, name=None, simulate=True): if not isinstance(width, int) or width < 0: - raise TypeError("Memory width must be a non-negative integer, not '{!r}'" + raise TypeError("Memory width must be a non-negative integer, not {!r}" .format(width)) if not isinstance(depth, int) or depth < 0: - raise TypeError("Memory depth must be a non-negative integer, not '{!r}'" + raise TypeError("Memory depth must be a non-negative integer, not {!r}" .format(depth)) self.name = name or tracer.get_var_name(depth=2, default="$memory") @@ -136,7 +136,7 @@ class WritePort(Elaboratable): if granularity is None: granularity = memory.width if not isinstance(granularity, int) or granularity < 0: - raise TypeError("Write port granularity must be a non-negative integer, not '{!r}'" + raise TypeError("Write port granularity must be a non-negative integer, not {!r}" .format(granularity)) if granularity > memory.width: raise ValueError("Write port granularity must not be greater than memory width " diff --git a/nmigen/hdl/xfrm.py b/nmigen/hdl/xfrm.py index 018b368..8ec0e10 100644 --- a/nmigen/hdl/xfrm.py +++ b/nmigen/hdl/xfrm.py @@ -83,7 +83,7 @@ class ValueVisitor(metaclass=ABCMeta): pass # :nocov: def on_unknown_value(self, value): - raise TypeError("Cannot transform value '{!r}'".format(value)) # :nocov: + raise TypeError("Cannot transform value {!r}".format(value)) # :nocov: def replace_value_src_loc(self, value, new_value): return True @@ -209,7 +209,7 @@ class StatementVisitor(metaclass=ABCMeta): pass # :nocov: def on_unknown_statement(self, stmt): - raise TypeError("Cannot transform statement '{!r}'".format(stmt)) # :nocov: + raise TypeError("Cannot transform statement {!r}".format(stmt)) # :nocov: def replace_statement_src_loc(self, stmt, new_stmt): return True @@ -321,7 +321,7 @@ class FragmentTransformer: value._transforms_.append(self) return value else: - raise AttributeError("Object '{!r}' cannot be elaborated".format(value)) + raise AttributeError("Object {!r} cannot be elaborated".format(value)) class TransformedElaboratable(Elaboratable): diff --git a/nmigen/lib/cdc.py b/nmigen/lib/cdc.py index 2bf1beb..9b7a4cc 100644 --- a/nmigen/lib/cdc.py +++ b/nmigen/lib/cdc.py @@ -9,7 +9,7 @@ __all__ += ["MultiReg"] def _check_stages(stages): if not isinstance(stages, int) or stages < 1: - raise TypeError("Synchronization stage count must be a positive integer, not '{!r}'" + raise TypeError("Synchronization stage count must be a positive integer, not {!r}" .format(stages)) if stages < 2: raise ValueError("Synchronization stage count may not safely be less than 2") diff --git a/nmigen/lib/fifo.py b/nmigen/lib/fifo.py index 3775bf8..da468b0 100644 --- a/nmigen/lib/fifo.py +++ b/nmigen/lib/fifo.py @@ -62,10 +62,10 @@ class FIFOInterface: def __init__(self, *, width, depth, fwft): if not isinstance(width, int) or width < 0: - raise TypeError("FIFO width must be a non-negative integer, not '{!r}'" + raise TypeError("FIFO width must be a non-negative integer, not {!r}" .format(width)) if not isinstance(depth, int) or depth < 0: - raise TypeError("FIFO depth must be a non-negative integer, not '{!r}'" + raise TypeError("FIFO depth must be a non-negative integer, not {!r}" .format(depth)) self.width = width self.depth = depth diff --git a/nmigen/lib/io.py b/nmigen/lib/io.py index 867c9b4..d2969b0 100644 --- a/nmigen/lib/io.py +++ b/nmigen/lib/io.py @@ -13,13 +13,13 @@ def pin_layout(width, dir, xdr=0): See :class:`Pin` for details. """ if not isinstance(width, int) or width < 1: - raise TypeError("Width must be a positive integer, not '{!r}'" + raise TypeError("Width must be a positive integer, not {!r}" .format(width)) if dir not in ("i", "o", "oe", "io"): - raise TypeError("Direction must be one of \"i\", \"o\", \"io\", or \"oe\", not '{!r}'""" + raise TypeError("Direction must be one of \"i\", \"o\", \"io\", or \"oe\", not {!r}""" .format(dir)) if not isinstance(xdr, int) or xdr < 0: - raise TypeError("Gearing ratio must be a non-negative integer, not '{!r}'" + raise TypeError("Gearing ratio must be a non-negative integer, not {!r}" .format(xdr)) fields = [] diff --git a/nmigen/test/test_hdl_ast.py b/nmigen/test/test_hdl_ast.py index 1a2bb17..653d0f7 100644 --- a/nmigen/test/test_hdl_ast.py +++ b/nmigen/test/test_hdl_ast.py @@ -105,9 +105,9 @@ class ConstTestCase(FHDLTestCase): self.assertEqual(Const(1, (4, True)).shape(), (4, True)) self.assertEqual(Const(0, (0, False)).shape(), (0, False)) - def test_shape_bad(self): + def test_shape_wrong(self): with self.assertRaises(TypeError, - msg="Width must be a non-negative integer, not '-1'"): + msg="Width must be a non-negative integer, not -1"): Const(1, -1) def test_normalization(self): @@ -392,10 +392,10 @@ class SliceTestCase(FHDLTestCase): def test_start_end_wrong(self): with self.assertRaises(TypeError, - msg="Slice start must be an integer, not ''x''"): + msg="Slice start must be an integer, not 'x'"): Slice(0, "x", 1) with self.assertRaises(TypeError, - msg="Slice end must be an integer, not ''x''"): + msg="Slice end must be an integer, not 'x'"): Slice(0, 1, "x") def test_start_end_out_of_range(self): @@ -430,7 +430,7 @@ class BitSelectTestCase(FHDLTestCase): s1 = self.c.bit_select(self.s, 2) self.assertEqual(s1.stride, 1) - def test_width_bad(self): + def test_width_wrong(self): with self.assertRaises(TypeError): self.c.bit_select(self.s, -1) @@ -452,7 +452,7 @@ class WordSelectTestCase(FHDLTestCase): s1 = self.c.word_select(self.s, 2) self.assertEqual(s1.stride, 2) - def test_width_bad(self): + def test_width_wrong(self): with self.assertRaises(TypeError): self.c.word_select(self.s, 0) with self.assertRaises(TypeError): @@ -595,9 +595,9 @@ class SignalTestCase(FHDLTestCase): d10 = Signal(max=1) self.assertEqual(d10.shape(), (0, False)) - def test_shape_bad(self): + def test_shape_wrong(self): with self.assertRaises(TypeError, - msg="Width must be a non-negative integer, not '-10'"): + msg="Width must be a non-negative integer, not -10"): Signal(-10) def test_min_max_deprecated(self): @@ -688,7 +688,7 @@ class ClockSignalTestCase(FHDLTestCase): self.assertEqual(s2.domain, "pix") with self.assertRaises(TypeError, - msg="Clock domain name must be a string, not '1'"): + msg="Clock domain name must be a string, not 1"): ClockSignal(1) def test_shape(self): @@ -712,7 +712,7 @@ class ResetSignalTestCase(FHDLTestCase): self.assertEqual(s2.domain, "pix") with self.assertRaises(TypeError, - msg="Clock domain name must be a string, not '1'"): + msg="Clock domain name must be a string, not 1"): ResetSignal(1) def test_shape(self): diff --git a/nmigen/test/test_hdl_dsl.py b/nmigen/test/test_hdl_dsl.py index 08bcc4c..e45a753 100644 --- a/nmigen/test/test_hdl_dsl.py +++ b/nmigen/test/test_hdl_dsl.py @@ -625,10 +625,10 @@ class DSLTestCase(FHDLTestCase): def test_submodule_wrong(self): m = Module() with self.assertRaises(TypeError, - msg="Trying to add '1', which does not implement .elaborate(), as a submodule"): + msg="Trying to add 1, which does not implement .elaborate(), as a submodule"): m.submodules.foo = 1 with self.assertRaises(TypeError, - msg="Trying to add '1', which does not implement .elaborate(), as a submodule"): + msg="Trying to add 1, which does not implement .elaborate(), as a submodule"): m.submodules += 1 def test_submodule_named_conflict(self): diff --git a/nmigen/test/test_hdl_ir.py b/nmigen/test/test_hdl_ir.py index 8bdfd5d..bcd56b5 100644 --- a/nmigen/test/test_hdl_ir.py +++ b/nmigen/test/test_hdl_ir.py @@ -15,13 +15,13 @@ class BadElaboratable(Elaboratable): class FragmentGetTestCase(FHDLTestCase): def test_get_wrong(self): with self.assertRaises(AttributeError, - msg="Object 'None' cannot be elaborated"): + msg="Object None cannot be elaborated"): Fragment.get(None, platform=None) with self.assertWarns(UserWarning, msg=".elaborate() returned None; missing return statement?"): with self.assertRaises(AttributeError, - msg="Object 'None' cannot be elaborated"): + msg="Object None cannot be elaborated"): Fragment.get(BadElaboratable(), platform=None) diff --git a/nmigen/test/test_hdl_mem.py b/nmigen/test/test_hdl_mem.py index 8e6dac9..8cf3bb1 100644 --- a/nmigen/test/test_hdl_mem.py +++ b/nmigen/test/test_hdl_mem.py @@ -19,10 +19,10 @@ class MemoryTestCase(FHDLTestCase): def test_geometry_wrong(self): with self.assertRaises(TypeError, - msg="Memory width must be a non-negative integer, not '-1'"): + msg="Memory width must be a non-negative integer, not -1"): m = Memory(width=-1, depth=4) with self.assertRaises(TypeError, - msg="Memory depth must be a non-negative integer, not '-1'"): + msg="Memory depth must be a non-negative integer, not -1"): m = Memory(width=8, depth=-1) def test_init(self): @@ -101,7 +101,7 @@ class MemoryTestCase(FHDLTestCase): def test_write_port_granularity_wrong(self): mem = Memory(width=8, depth=4) with self.assertRaises(TypeError, - msg="Write port granularity must be a non-negative integer, not '-1'"): + msg="Write port granularity must be a non-negative integer, not -1"): mem.write_port(granularity=-1) with self.assertRaises(ValueError, msg="Write port granularity must not be greater than memory width (10 > 8)"): diff --git a/nmigen/test/test_lib_cdc.py b/nmigen/test/test_lib_cdc.py index 1178508..23ebed5 100644 --- a/nmigen/test/test_lib_cdc.py +++ b/nmigen/test/test_lib_cdc.py @@ -7,7 +7,7 @@ from ..lib.cdc import * class FFSynchronizerTestCase(FHDLTestCase): def test_stages_wrong(self): with self.assertRaises(TypeError, - msg="Synchronization stage count must be a positive integer, not '0'"): + msg="Synchronization stage count must be a positive integer, not 0"): FFSynchronizer(Signal(), Signal(), stages=0) with self.assertRaises(ValueError, msg="Synchronization stage count may not safely be less than 2"): @@ -53,7 +53,7 @@ class FFSynchronizerTestCase(FHDLTestCase): class ResetSynchronizerTestCase(FHDLTestCase): def test_stages_wrong(self): with self.assertRaises(TypeError, - msg="Synchronization stage count must be a positive integer, not '0'"): + msg="Synchronization stage count must be a positive integer, not 0"): ResetSynchronizer(Signal(), stages=0) with self.assertRaises(ValueError, msg="Synchronization stage count may not safely be less than 2"): diff --git a/nmigen/test/test_lib_fifo.py b/nmigen/test/test_lib_fifo.py index d116752..1b3a919 100644 --- a/nmigen/test/test_lib_fifo.py +++ b/nmigen/test/test_lib_fifo.py @@ -8,10 +8,10 @@ from ..lib.fifo import * class FIFOTestCase(FHDLTestCase): def test_depth_wrong(self): with self.assertRaises(TypeError, - msg="FIFO width must be a non-negative integer, not '-1'"): + msg="FIFO width must be a non-negative integer, not -1"): FIFOInterface(width=-1, depth=8, fwft=True) with self.assertRaises(TypeError, - msg="FIFO depth must be a non-negative integer, not '-1'"): + msg="FIFO depth must be a non-negative integer, not -1"): FIFOInterface(width=8, depth=-1, fwft=True) def test_sync_depth(self): diff --git a/nmigen/test/test_sim.py b/nmigen/test/test_sim.py index f818069..ed837a3 100644 --- a/nmigen/test/test_sim.py +++ b/nmigen/test/test_sim.py @@ -426,7 +426,7 @@ class SimulatorIntegrationTestCase(FHDLTestCase): def test_add_process_wrong(self): with self.assertSimulation(Module()) as sim: with self.assertRaises(TypeError, - msg="Cannot add a process '1' because it is not a generator or " + msg="Cannot add a process 1 because it is not a generator or " "a generator function"): sim.add_process(1) @@ -458,7 +458,7 @@ class SimulatorIntegrationTestCase(FHDLTestCase): with self.assertSimulation(self.m) as sim: def process(): with self.assertRaisesRegex(ValueError, - regex=r"Process '.+?' sent a request to set signal '\(sig s\)', " + regex=r"Process .+? sent a request to set signal \(sig s\), " r"which is not a part of simulation"): yield self.s.eq(0) yield Delay() @@ -469,7 +469,7 @@ class SimulatorIntegrationTestCase(FHDLTestCase): with self.assertSimulation(self.m) as sim: def process(): with self.assertRaisesRegex(ValueError, - regex=r"Process '.+?' sent a request to set signal '\(sig o\)', " + regex=r"Process .+? sent a request to set signal \(sig o\), " r"which is a part of combinatorial assignment in simulation"): yield self.o.eq(0) yield Delay() @@ -479,7 +479,7 @@ class SimulatorIntegrationTestCase(FHDLTestCase): with self.assertSimulation(Module()) as sim: def process(): with self.assertRaisesRegex(TypeError, - regex=r"Received unsupported command '1' from process '.+?'"): + regex=r"Received unsupported command 1 from process .+?"): yield 1 yield Delay() sim.add_process(process)