From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 6 Nov 2018 11:20:34 +0000 (+0000)
Subject: elwidth-ify rv_sl and rv_sr
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1d8f0ca59d3451f84be6f171f40d3ca765e132d0;p=riscv-isa-sim.git

elwidth-ify rv_sl and rv_sr
---

diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc
index 12ae220..5b410c5 100644
--- a/riscv/sv_insn_redirect.cc
+++ b/riscv/sv_insn_redirect.cc
@@ -541,12 +541,26 @@ sv_reg_t sv_proc_t::rv_xor(sv_reg_t const & lhs, sv_reg_t const & rhs)
 
 sv_reg_t sv_proc_t::rv_sl(sv_reg_t const & lhs, sv_reg_t const & rhs)
 {
-    return lhs << rhs;
+    uint8_t bitwidth = _insn->src_bitwidth;
+    uint64_t vlhs = 0;
+    uint64_t vrhs = 0;
+    if (rv_int_op_prepare(lhs, rhs, vlhs, vrhs, bitwidth)) {
+        return lhs << rhs;
+    }
+    uint64_t result = vlhs << vrhs;
+    return rv_int_op_finish(lhs, rhs, result, bitwidth);
 }
 
 sv_reg_t sv_proc_t::rv_sr(sv_reg_t const & lhs, sv_reg_t const & rhs)
 {
-    return lhs >> rhs;
+    uint8_t bitwidth = _insn->src_bitwidth;
+    uint64_t vlhs = 0;
+    uint64_t vrhs = 0;
+    if (rv_int_op_prepare(lhs, rhs, vlhs, vrhs, bitwidth)) {
+        return lhs >> rhs;
+    }
+    uint64_t result = vlhs >> vrhs;
+    return rv_int_op_finish(lhs, rhs, result, bitwidth);
 }
 
 bool sv_proc_t::rv_lt(sv_reg_t const & lhs, sv_reg_t const & rhs)