From: Luke Kenneth Casson Leighton Date: Sun, 5 Aug 2018 11:43:45 +0000 (+0100) Subject: add interrupt handling section X-Git-Tag: convert-csv-opcode-to-binary~5035 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1d9f60735abdb0a5a5c5bfc5c4a5da28bcb1034c;p=libreriscv.git add interrupt handling section --- diff --git a/interrupts/interrupt_handling.mdwn b/interrupts/interrupt_handling.mdwn index a0907bbf6..57cfed24d 100644 --- a/interrupts/interrupt_handling.mdwn +++ b/interrupts/interrupt_handling.mdwn @@ -15,17 +15,20 @@ familiar with markdown or editing of wikis please contact luke.leighton@gmail.com, sending the appropriate text, for inclusion here. * **Libre-RISCV Shakti M-Class**: a 300-400 pin SoC with almost a hundred - separate and distinct "slow" (below 160mhz) peripherals that need nothing - particularly special in the way of fast latency IRQs, just lots of them. - Five UARTs, each requiring one IRQ line; Four I2C peripherals, each - requiring two IRQ lines, Multiple Quad SPI interfaces requring **six** - IRQ lines (each!), the number of IRQ lines required to cover such - a significant number of peripherals begins to add up quite rapidly. - However despite this, the PLIC as it stands (privspec-v-1.10 chapter 7) - actually covers the requirements quite nicely, as long as it can cope - with large numbers *of* IRQ lines (which it can). Thus the Shakti - PLIC Peripheral code has been modified from its original (which could - handle up to XLEN separate lines) to a hierarchical arrangement that - can handle up to 1024 separate and distinct IRQs + separate and distinct "slow" (below 160mhz) peripherals that need + nothing particularly special in the way of fast latency IRQs, just lots + of them. Five UARTs, each requiring one IRQ line; Four I2C peripherals, + each requiring two IRQ lines, Multiple Quad SPI interfaces requring + **six** IRQ lines (each!), and 32 "EINT" lines (general-purpose + external interrupt) which are intended for mundane purposes such as + "lid opened", or "volume key pressed" and "headphone jack inserted", + the number of IRQ lines required to cover such a significant number + of peripherals begins to add up quite rapidly. However despite this, + the PLIC as it stands (privspec-v-1.10 chapter 7) actually covers the + requirements quite nicely, as long as it can cope with large numbers + *of* IRQ lines (which it can). Thus the Shakti PLIC Peripheral code + has been modified from its original (which could handle up to XLEN + separate lines) to a hierarchical arrangement that can handle up to + 1024 separate and distinct IRQs