From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Thu, 28 Feb 2019 21:56:45 +0000 (-0800)
Subject: Remove SRL16/32 from cells_xtra
X-Git-Tag: yosys-0.9~171^2~66
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1da090966263318c46dd1d91d2f1f4d11238c2c1;p=yosys.git

Remove SRL16/32 from cells_xtra
---

diff --git a/techlibs/xilinx/cells_xtra.sh b/techlibs/xilinx/cells_xtra.sh
index 0480410f5..8cc90d1f2 100644
--- a/techlibs/xilinx/cells_xtra.sh
+++ b/techlibs/xilinx/cells_xtra.sh
@@ -134,8 +134,8 @@ function xtract_cell_decl()
 	xtract_cell_decl ROM256X1
 	xtract_cell_decl ROM32X1
 	xtract_cell_decl ROM64X1
-	xtract_cell_decl SRL16E
-	xtract_cell_decl SRLC32E
+	#xtract_cell_decl SRL16E
+	#xtract_cell_decl SRLC32E
 	xtract_cell_decl STARTUPE2
 	xtract_cell_decl USR_ACCESSE2
 	xtract_cell_decl XADC
diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v
index 8d8b91ddc..21db6a6bd 100644
--- a/techlibs/xilinx/cells_xtra.v
+++ b/techlibs/xilinx/cells_xtra.v
@@ -3824,22 +3824,6 @@ module ROM64X1 (...);
     input A0, A1, A2, A3, A4, A5;
 endmodule
 
-module SRL16E (...);
-    parameter [15:0] INIT = 16'h0000;
-    parameter [0:0] IS_CLK_INVERTED = 1'b0;
-    output Q;
-    input A0, A1, A2, A3, CE, CLK, D;
-endmodule
-
-module SRLC32E (...);
-    parameter [31:0] INIT = 32'h00000000;
-    parameter [0:0] IS_CLK_INVERTED = 1'b0;
-    output Q;
-    output Q31;
-    input [4:0] A;
-    input CE, CLK, D;
-endmodule
-
 module STARTUPE2 (...);
     parameter PROG_USR = "FALSE";
     parameter real SIM_CCLK_FREQ = 0.0;