From: Kenneth Graunke Date: Tue, 4 Apr 2017 18:45:08 +0000 (-0700) Subject: i965/drm: Drop intel_chipset.h in favor of using gen_device_info. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1dc02da6d79eef0450b43a90fddd72342140f0db;p=mesa.git i965/drm: Drop intel_chipset.h in favor of using gen_device_info. This moves the PCI ID detection to intel_screen.c and makes drm_bacon_bufmgr_gem_init() take a devinfo pointer. We also drop the HAS_LLC query stuff - devinfo has that info already, without kernel queries, and it makes no sense to have two has_llc flags set by different mechanisms. Reviewed-by: Chris Wilson Acked-by: Jason Ekstrand --- diff --git a/src/mesa/drivers/dri/i965/Makefile.sources b/src/mesa/drivers/dri/i965/Makefile.sources index 9068bcdde7a..9b550dc17cc 100644 --- a/src/mesa/drivers/dri/i965/Makefile.sources +++ b/src/mesa/drivers/dri/i965/Makefile.sources @@ -132,7 +132,6 @@ i965_FILES = \ intel_buffers.c \ intel_buffers.h \ intel_bufmgr_gem.c \ - intel_chipset.h \ intel_copy_image.c \ intel_extensions.c \ intel_fbo.c \ diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.h b/src/mesa/drivers/dri/i965/brw_bufmgr.h index 1e47f75b4a5..11c02604f12 100644 --- a/src/mesa/drivers/dri/i965/brw_bufmgr.h +++ b/src/mesa/drivers/dri/i965/brw_bufmgr.h @@ -42,6 +42,8 @@ extern "C" { #endif +struct gen_device_info; + typedef struct _drm_bacon_bufmgr drm_bacon_bufmgr; typedef struct _drm_bacon_context drm_bacon_context; typedef struct _drm_bacon_bo drm_bacon_bo; @@ -293,7 +295,8 @@ int drm_bacon_bo_is_reusable(drm_bacon_bo *bo); int drm_bacon_bo_references(drm_bacon_bo *bo, drm_bacon_bo *target_bo); /* drm_bacon_bufmgr_gem.c */ -drm_bacon_bufmgr *drm_bacon_bufmgr_gem_init(int fd, int batch_size); +drm_bacon_bufmgr *drm_bacon_bufmgr_gem_init(struct gen_device_info *devinfo, + int fd, int batch_size); drm_bacon_bo *drm_bacon_bo_gem_create_from_name(drm_bacon_bufmgr *bufmgr, const char *name, unsigned int handle); @@ -316,7 +319,6 @@ int drm_bacon_gem_bo_get_reloc_count(drm_bacon_bo *bo); void drm_bacon_gem_bo_clear_relocs(drm_bacon_bo *bo, int start); void drm_bacon_gem_bo_start_gtt_access(drm_bacon_bo *bo, int write_enable); -int drm_bacon_bufmgr_gem_get_devid(drm_bacon_bufmgr *bufmgr); int drm_bacon_gem_bo_wait(drm_bacon_bo *bo, int64_t timeout_ns); drm_bacon_context *drm_bacon_gem_context_create(drm_bacon_bufmgr *bufmgr); diff --git a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c index 40ad89f87a1..7c8598c1fde 100644 --- a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c +++ b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c @@ -57,12 +57,12 @@ #define ETIME ETIMEDOUT #endif #include "common/gen_debug.h" +#include "common/gen_device_info.h" #include "libdrm_macros.h" #include "main/macros.h" #include "util/macros.h" #include "util/list.h" #include "brw_bufmgr.h" -#include "intel_chipset.h" #include "string.h" #include "i915_drm.h" @@ -146,8 +146,6 @@ typedef struct _drm_bacon_bufmgr { int vma_count, vma_open, vma_max; uint64_t gtt_size; - int pci_device; - int gen; unsigned int has_bsd : 1; unsigned int has_blt : 1; unsigned int has_llc : 1; @@ -2636,71 +2634,6 @@ drm_bacon_bufmgr_gem_set_vma_cache_size(drm_bacon_bufmgr *bufmgr, int limit) drm_bacon_gem_bo_purge_vma_cache(bufmgr); } -static int -parse_devid_override(const char *devid_override) -{ - static const struct { - const char *name; - int pci_id; - } name_map[] = { - { "brw", PCI_CHIP_I965_GM }, - { "g4x", PCI_CHIP_GM45_GM }, - { "ilk", PCI_CHIP_ILD_G }, - { "snb", PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS }, - { "ivb", PCI_CHIP_IVYBRIDGE_S_GT2 }, - { "hsw", PCI_CHIP_HASWELL_CRW_E_GT3 }, - { "byt", PCI_CHIP_VALLEYVIEW_3 }, - { "bdw", 0x1620 | BDW_ULX }, - { "skl", PCI_CHIP_SKYLAKE_DT_GT2 }, - { "kbl", PCI_CHIP_KABYLAKE_DT_GT2 }, - }; - unsigned int i; - - for (i = 0; i < ARRAY_SIZE(name_map); i++) { - if (!strcmp(name_map[i].name, devid_override)) - return name_map[i].pci_id; - } - - return strtod(devid_override, NULL); -} - -/** - * Get the PCI ID for the device. This can be overridden by setting the - * INTEL_DEVID_OVERRIDE environment variable to the desired ID. - */ -static int -get_pci_device_id(drm_bacon_bufmgr *bufmgr) -{ - char *devid_override; - int devid = 0; - int ret; - drm_i915_getparam_t gp; - - if (geteuid() == getuid()) { - devid_override = getenv("INTEL_DEVID_OVERRIDE"); - if (devid_override) { - bufmgr->no_exec = true; - return parse_devid_override(devid_override); - } - } - - memclear(gp); - gp.param = I915_PARAM_CHIPSET_ID; - gp.value = &devid; - ret = drmIoctl(bufmgr->fd, DRM_IOCTL_I915_GETPARAM, &gp); - if (ret) { - fprintf(stderr, "get chip id failed: %d [%d]\n", ret, errno); - fprintf(stderr, "param: %d, val: %d\n", gp.param, *gp.value); - } - return devid; -} - -int -drm_bacon_bufmgr_gem_get_devid(drm_bacon_bufmgr *bufmgr) -{ - return bufmgr->pci_device; -} - drm_bacon_context * drm_bacon_gem_context_create(drm_bacon_bufmgr *bufmgr) { @@ -2982,7 +2915,8 @@ void *drm_bacon_gem_bo_map__wc(drm_bacon_bo *bo) * \param fd File descriptor of the opened DRM device. */ drm_bacon_bufmgr * -drm_bacon_bufmgr_gem_init(int fd, int batch_size) +drm_bacon_bufmgr_gem_init(struct gen_device_info *devinfo, + int fd, int batch_size) { drm_bacon_bufmgr *bufmgr; struct drm_i915_gem_get_aperture aperture; @@ -3012,26 +2946,6 @@ drm_bacon_bufmgr_gem_init(int fd, int batch_size) drmIoctl(bufmgr->fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture); bufmgr->gtt_size = aperture.aper_available_size; - bufmgr->pci_device = get_pci_device_id(bufmgr); - - if (IS_GEN4(bufmgr->pci_device)) - bufmgr->gen = 4; - else if (IS_GEN5(bufmgr->pci_device)) - bufmgr->gen = 5; - else if (IS_GEN6(bufmgr->pci_device)) - bufmgr->gen = 6; - else if (IS_GEN7(bufmgr->pci_device)) - bufmgr->gen = 7; - else if (IS_GEN8(bufmgr->pci_device)) - bufmgr->gen = 8; - else if (IS_GEN9(bufmgr->pci_device)) - bufmgr->gen = 9; - else { - free(bufmgr); - bufmgr = NULL; - goto exit; - } - memclear(gp); gp.value = &tmp; @@ -3047,16 +2961,7 @@ drm_bacon_bufmgr_gem_init(int fd, int batch_size) ret = drmIoctl(bufmgr->fd, DRM_IOCTL_I915_GETPARAM, &gp); bufmgr->has_exec_async = ret == 0; - gp.param = I915_PARAM_HAS_LLC; - ret = drmIoctl(bufmgr->fd, DRM_IOCTL_I915_GETPARAM, &gp); - if (ret != 0) { - /* Kernel does not supports HAS_LLC query, fallback to GPU - * generation detection and assume that we have LLC on GEN6/7 - */ - bufmgr->has_llc = (IS_GEN6(bufmgr->pci_device) | - IS_GEN7(bufmgr->pci_device)); - } else - bufmgr->has_llc = *gp.value; + bufmgr->has_llc = devinfo->has_llc; gp.param = I915_PARAM_HAS_VEBOX; ret = drmIoctl(bufmgr->fd, DRM_IOCTL_I915_GETPARAM, &gp); diff --git a/src/mesa/drivers/dri/i965/intel_chipset.h b/src/mesa/drivers/dri/i965/intel_chipset.h deleted file mode 100644 index 41fc0da061c..00000000000 --- a/src/mesa/drivers/dri/i965/intel_chipset.h +++ /dev/null @@ -1,469 +0,0 @@ -/* - * - * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sub license, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. - * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef _INTEL_CHIPSET_H -#define _INTEL_CHIPSET_H - -#define PCI_CHIP_I810 0x7121 -#define PCI_CHIP_I810_DC100 0x7123 -#define PCI_CHIP_I810_E 0x7125 -#define PCI_CHIP_I815 0x1132 - -#define PCI_CHIP_I830_M 0x3577 -#define PCI_CHIP_845_G 0x2562 -#define PCI_CHIP_I855_GM 0x3582 -#define PCI_CHIP_I865_G 0x2572 - -#define PCI_CHIP_I915_G 0x2582 -#define PCI_CHIP_E7221_G 0x258A -#define PCI_CHIP_I915_GM 0x2592 -#define PCI_CHIP_I945_G 0x2772 -#define PCI_CHIP_I945_GM 0x27A2 -#define PCI_CHIP_I945_GME 0x27AE - -#define PCI_CHIP_Q35_G 0x29B2 -#define PCI_CHIP_G33_G 0x29C2 -#define PCI_CHIP_Q33_G 0x29D2 - -#define PCI_CHIP_IGD_GM 0xA011 -#define PCI_CHIP_IGD_G 0xA001 - -#define IS_IGDGM(devid) ((devid) == PCI_CHIP_IGD_GM) -#define IS_IGDG(devid) ((devid) == PCI_CHIP_IGD_G) -#define IS_IGD(devid) (IS_IGDG(devid) || IS_IGDGM(devid)) - -#define PCI_CHIP_I965_G 0x29A2 -#define PCI_CHIP_I965_Q 0x2992 -#define PCI_CHIP_I965_G_1 0x2982 -#define PCI_CHIP_I946_GZ 0x2972 -#define PCI_CHIP_I965_GM 0x2A02 -#define PCI_CHIP_I965_GME 0x2A12 - -#define PCI_CHIP_GM45_GM 0x2A42 - -#define PCI_CHIP_IGD_E_G 0x2E02 -#define PCI_CHIP_Q45_G 0x2E12 -#define PCI_CHIP_G45_G 0x2E22 -#define PCI_CHIP_G41_G 0x2E32 - -#define PCI_CHIP_ILD_G 0x0042 -#define PCI_CHIP_ILM_G 0x0046 - -#define PCI_CHIP_SANDYBRIDGE_GT1 0x0102 /* desktop */ -#define PCI_CHIP_SANDYBRIDGE_GT2 0x0112 -#define PCI_CHIP_SANDYBRIDGE_GT2_PLUS 0x0122 -#define PCI_CHIP_SANDYBRIDGE_M_GT1 0x0106 /* mobile */ -#define PCI_CHIP_SANDYBRIDGE_M_GT2 0x0116 -#define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS 0x0126 -#define PCI_CHIP_SANDYBRIDGE_S 0x010A /* server */ - -#define PCI_CHIP_IVYBRIDGE_GT1 0x0152 /* desktop */ -#define PCI_CHIP_IVYBRIDGE_GT2 0x0162 -#define PCI_CHIP_IVYBRIDGE_M_GT1 0x0156 /* mobile */ -#define PCI_CHIP_IVYBRIDGE_M_GT2 0x0166 -#define PCI_CHIP_IVYBRIDGE_S 0x015a /* server */ -#define PCI_CHIP_IVYBRIDGE_S_GT2 0x016a /* server */ - -#define PCI_CHIP_HASWELL_GT1 0x0402 /* Desktop */ -#define PCI_CHIP_HASWELL_GT2 0x0412 -#define PCI_CHIP_HASWELL_GT3 0x0422 -#define PCI_CHIP_HASWELL_M_GT1 0x0406 /* Mobile */ -#define PCI_CHIP_HASWELL_M_GT2 0x0416 -#define PCI_CHIP_HASWELL_M_GT3 0x0426 -#define PCI_CHIP_HASWELL_S_GT1 0x040A /* Server */ -#define PCI_CHIP_HASWELL_S_GT2 0x041A -#define PCI_CHIP_HASWELL_S_GT3 0x042A -#define PCI_CHIP_HASWELL_B_GT1 0x040B /* Reserved */ -#define PCI_CHIP_HASWELL_B_GT2 0x041B -#define PCI_CHIP_HASWELL_B_GT3 0x042B -#define PCI_CHIP_HASWELL_E_GT1 0x040E /* Reserved */ -#define PCI_CHIP_HASWELL_E_GT2 0x041E -#define PCI_CHIP_HASWELL_E_GT3 0x042E -#define PCI_CHIP_HASWELL_SDV_GT1 0x0C02 /* Desktop */ -#define PCI_CHIP_HASWELL_SDV_GT2 0x0C12 -#define PCI_CHIP_HASWELL_SDV_GT3 0x0C22 -#define PCI_CHIP_HASWELL_SDV_M_GT1 0x0C06 /* Mobile */ -#define PCI_CHIP_HASWELL_SDV_M_GT2 0x0C16 -#define PCI_CHIP_HASWELL_SDV_M_GT3 0x0C26 -#define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A /* Server */ -#define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A -#define PCI_CHIP_HASWELL_SDV_S_GT3 0x0C2A -#define PCI_CHIP_HASWELL_SDV_B_GT1 0x0C0B /* Reserved */ -#define PCI_CHIP_HASWELL_SDV_B_GT2 0x0C1B -#define PCI_CHIP_HASWELL_SDV_B_GT3 0x0C2B -#define PCI_CHIP_HASWELL_SDV_E_GT1 0x0C0E /* Reserved */ -#define PCI_CHIP_HASWELL_SDV_E_GT2 0x0C1E -#define PCI_CHIP_HASWELL_SDV_E_GT3 0x0C2E -#define PCI_CHIP_HASWELL_ULT_GT1 0x0A02 /* Desktop */ -#define PCI_CHIP_HASWELL_ULT_GT2 0x0A12 -#define PCI_CHIP_HASWELL_ULT_GT3 0x0A22 -#define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06 /* Mobile */ -#define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16 -#define PCI_CHIP_HASWELL_ULT_M_GT3 0x0A26 -#define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */ -#define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A -#define PCI_CHIP_HASWELL_ULT_S_GT3 0x0A2A -#define PCI_CHIP_HASWELL_ULT_B_GT1 0x0A0B /* Reserved */ -#define PCI_CHIP_HASWELL_ULT_B_GT2 0x0A1B -#define PCI_CHIP_HASWELL_ULT_B_GT3 0x0A2B -#define PCI_CHIP_HASWELL_ULT_E_GT1 0x0A0E /* Reserved */ -#define PCI_CHIP_HASWELL_ULT_E_GT2 0x0A1E -#define PCI_CHIP_HASWELL_ULT_E_GT3 0x0A2E -#define PCI_CHIP_HASWELL_CRW_GT1 0x0D02 /* Desktop */ -#define PCI_CHIP_HASWELL_CRW_GT2 0x0D12 -#define PCI_CHIP_HASWELL_CRW_GT3 0x0D22 -#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D06 /* Mobile */ -#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D16 -#define PCI_CHIP_HASWELL_CRW_M_GT3 0x0D26 -#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A /* Server */ -#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A -#define PCI_CHIP_HASWELL_CRW_S_GT3 0x0D2A -#define PCI_CHIP_HASWELL_CRW_B_GT1 0x0D0B /* Reserved */ -#define PCI_CHIP_HASWELL_CRW_B_GT2 0x0D1B -#define PCI_CHIP_HASWELL_CRW_B_GT3 0x0D2B -#define PCI_CHIP_HASWELL_CRW_E_GT1 0x0D0E /* Reserved */ -#define PCI_CHIP_HASWELL_CRW_E_GT2 0x0D1E -#define PCI_CHIP_HASWELL_CRW_E_GT3 0x0D2E -#define BDW_SPARE 0x2 -#define BDW_ULT 0x6 -#define BDW_SERVER 0xa -#define BDW_IRIS 0xb -#define BDW_WORKSTATION 0xd -#define BDW_ULX 0xe - -#define PCI_CHIP_VALLEYVIEW_PO 0x0f30 /* VLV PO board */ -#define PCI_CHIP_VALLEYVIEW_1 0x0f31 -#define PCI_CHIP_VALLEYVIEW_2 0x0f32 -#define PCI_CHIP_VALLEYVIEW_3 0x0f33 - -#define PCI_CHIP_CHERRYVIEW_0 0x22b0 -#define PCI_CHIP_CHERRYVIEW_1 0x22b1 -#define PCI_CHIP_CHERRYVIEW_2 0x22b2 -#define PCI_CHIP_CHERRYVIEW_3 0x22b3 - -#define PCI_CHIP_SKYLAKE_DT_GT1 0x1902 -#define PCI_CHIP_SKYLAKE_ULT_GT1 0x1906 -#define PCI_CHIP_SKYLAKE_SRV_GT1 0x190A /* Reserved */ -#define PCI_CHIP_SKYLAKE_H_GT1 0x190B -#define PCI_CHIP_SKYLAKE_ULX_GT1 0x190E /* Reserved */ -#define PCI_CHIP_SKYLAKE_DT_GT2 0x1912 -#define PCI_CHIP_SKYLAKE_FUSED0_GT2 0x1913 /* Reserved */ -#define PCI_CHIP_SKYLAKE_FUSED1_GT2 0x1915 /* Reserved */ -#define PCI_CHIP_SKYLAKE_ULT_GT2 0x1916 -#define PCI_CHIP_SKYLAKE_FUSED2_GT2 0x1917 /* Reserved */ -#define PCI_CHIP_SKYLAKE_SRV_GT2 0x191A /* Reserved */ -#define PCI_CHIP_SKYLAKE_HALO_GT2 0x191B -#define PCI_CHIP_SKYLAKE_WKS_GT2 0x191D -#define PCI_CHIP_SKYLAKE_ULX_GT2 0x191E -#define PCI_CHIP_SKYLAKE_MOBILE_GT2 0x1921 /* Reserved */ -#define PCI_CHIP_SKYLAKE_ULT_GT3_0 0x1923 -#define PCI_CHIP_SKYLAKE_ULT_GT3_1 0x1926 -#define PCI_CHIP_SKYLAKE_ULT_GT3_2 0x1927 -#define PCI_CHIP_SKYLAKE_SRV_GT4 0x192A -#define PCI_CHIP_SKYLAKE_HALO_GT3 0x192B /* Reserved */ -#define PCI_CHIP_SKYLAKE_SRV_GT3 0x192D -#define PCI_CHIP_SKYLAKE_DT_GT4 0x1932 -#define PCI_CHIP_SKYLAKE_SRV_GT4X 0x193A -#define PCI_CHIP_SKYLAKE_H_GT4 0x193B -#define PCI_CHIP_SKYLAKE_WKS_GT4 0x193D - -#define PCI_CHIP_KABYLAKE_ULT_GT2 0x5916 -#define PCI_CHIP_KABYLAKE_ULT_GT1_5 0x5913 -#define PCI_CHIP_KABYLAKE_ULT_GT1 0x5906 -#define PCI_CHIP_KABYLAKE_ULT_GT3_0 0x5923 -#define PCI_CHIP_KABYLAKE_ULT_GT3_1 0x5926 -#define PCI_CHIP_KABYLAKE_ULT_GT3_2 0x5927 -#define PCI_CHIP_KABYLAKE_ULT_GT2F 0x5921 -#define PCI_CHIP_KABYLAKE_ULX_GT1_5 0x5915 -#define PCI_CHIP_KABYLAKE_ULX_GT1 0x590E -#define PCI_CHIP_KABYLAKE_ULX_GT2 0x591E -#define PCI_CHIP_KABYLAKE_DT_GT2 0x5912 -#define PCI_CHIP_KABYLAKE_DT_GT1_5 0x5917 -#define PCI_CHIP_KABYLAKE_DT_GT1 0x5902 -#define PCI_CHIP_KABYLAKE_HALO_GT2 0x591B -#define PCI_CHIP_KABYLAKE_HALO_GT4 0x593B -#define PCI_CHIP_KABYLAKE_HALO_GT1_0 0x5908 -#define PCI_CHIP_KABYLAKE_HALO_GT1_1 0x590B -#define PCI_CHIP_KABYLAKE_SRV_GT2 0x591A -#define PCI_CHIP_KABYLAKE_SRV_GT1 0x590A -#define PCI_CHIP_KABYLAKE_WKS_GT2 0x591D - -#define PCI_CHIP_BROXTON_0 0x0A84 -#define PCI_CHIP_BROXTON_1 0x1A84 -#define PCI_CHIP_BROXTON_2 0x5A84 -#define PCI_CHIP_BROXTON_3 0x1A85 -#define PCI_CHIP_BROXTON_4 0x5A85 - -#define PCI_CHIP_GLK 0x3184 -#define PCI_CHIP_GLK_2X6 0x3185 - -#define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \ - (devid) == PCI_CHIP_I915_GM || \ - (devid) == PCI_CHIP_I945_GM || \ - (devid) == PCI_CHIP_I945_GME || \ - (devid) == PCI_CHIP_I965_GM || \ - (devid) == PCI_CHIP_I965_GME || \ - (devid) == PCI_CHIP_GM45_GM || IS_IGD(devid) || \ - (devid) == PCI_CHIP_IVYBRIDGE_M_GT1 || \ - (devid) == PCI_CHIP_IVYBRIDGE_M_GT2) - -#define IS_G45(devid) ((devid) == PCI_CHIP_IGD_E_G || \ - (devid) == PCI_CHIP_Q45_G || \ - (devid) == PCI_CHIP_G45_G || \ - (devid) == PCI_CHIP_G41_G) -#define IS_GM45(devid) ((devid) == PCI_CHIP_GM45_GM) -#define IS_G4X(devid) (IS_G45(devid) || IS_GM45(devid)) - -#define IS_ILD(devid) ((devid) == PCI_CHIP_ILD_G) -#define IS_ILM(devid) ((devid) == PCI_CHIP_ILM_G) - -#define IS_915(devid) ((devid) == PCI_CHIP_I915_G || \ - (devid) == PCI_CHIP_E7221_G || \ - (devid) == PCI_CHIP_I915_GM) - -#define IS_945GM(devid) ((devid) == PCI_CHIP_I945_GM || \ - (devid) == PCI_CHIP_I945_GME) - -#define IS_945(devid) ((devid) == PCI_CHIP_I945_G || \ - (devid) == PCI_CHIP_I945_GM || \ - (devid) == PCI_CHIP_I945_GME || \ - IS_G33(devid)) - -#define IS_G33(devid) ((devid) == PCI_CHIP_G33_G || \ - (devid) == PCI_CHIP_Q33_G || \ - (devid) == PCI_CHIP_Q35_G || IS_IGD(devid)) - -#define IS_GEN2(devid) ((devid) == PCI_CHIP_I830_M || \ - (devid) == PCI_CHIP_845_G || \ - (devid) == PCI_CHIP_I855_GM || \ - (devid) == PCI_CHIP_I865_G) - -#define IS_GEN3(devid) (IS_945(devid) || IS_915(devid)) - -#define IS_GEN4(devid) ((devid) == PCI_CHIP_I965_G || \ - (devid) == PCI_CHIP_I965_Q || \ - (devid) == PCI_CHIP_I965_G_1 || \ - (devid) == PCI_CHIP_I965_GM || \ - (devid) == PCI_CHIP_I965_GME || \ - (devid) == PCI_CHIP_I946_GZ || \ - IS_G4X(devid)) - -#define IS_GEN5(devid) (IS_ILD(devid) || IS_ILM(devid)) - -#define IS_GEN6(devid) ((devid) == PCI_CHIP_SANDYBRIDGE_GT1 || \ - (devid) == PCI_CHIP_SANDYBRIDGE_GT2 || \ - (devid) == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \ - (devid) == PCI_CHIP_SANDYBRIDGE_M_GT1 || \ - (devid) == PCI_CHIP_SANDYBRIDGE_M_GT2 || \ - (devid) == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \ - (devid) == PCI_CHIP_SANDYBRIDGE_S) - -#define IS_GEN7(devid) (IS_IVYBRIDGE(devid) || \ - IS_HASWELL(devid) || \ - IS_VALLEYVIEW(devid)) - -#define IS_IVYBRIDGE(devid) ((devid) == PCI_CHIP_IVYBRIDGE_GT1 || \ - (devid) == PCI_CHIP_IVYBRIDGE_GT2 || \ - (devid) == PCI_CHIP_IVYBRIDGE_M_GT1 || \ - (devid) == PCI_CHIP_IVYBRIDGE_M_GT2 || \ - (devid) == PCI_CHIP_IVYBRIDGE_S || \ - (devid) == PCI_CHIP_IVYBRIDGE_S_GT2) - -#define IS_VALLEYVIEW(devid) ((devid) == PCI_CHIP_VALLEYVIEW_PO || \ - (devid) == PCI_CHIP_VALLEYVIEW_1 || \ - (devid) == PCI_CHIP_VALLEYVIEW_2 || \ - (devid) == PCI_CHIP_VALLEYVIEW_3) - -#define IS_HSW_GT1(devid) ((devid) == PCI_CHIP_HASWELL_GT1 || \ - (devid) == PCI_CHIP_HASWELL_M_GT1 || \ - (devid) == PCI_CHIP_HASWELL_S_GT1 || \ - (devid) == PCI_CHIP_HASWELL_B_GT1 || \ - (devid) == PCI_CHIP_HASWELL_E_GT1 || \ - (devid) == PCI_CHIP_HASWELL_SDV_GT1 || \ - (devid) == PCI_CHIP_HASWELL_SDV_M_GT1 || \ - (devid) == PCI_CHIP_HASWELL_SDV_S_GT1 || \ - (devid) == PCI_CHIP_HASWELL_SDV_B_GT1 || \ - (devid) == PCI_CHIP_HASWELL_SDV_E_GT1 || \ - (devid) == PCI_CHIP_HASWELL_ULT_GT1 || \ - (devid) == PCI_CHIP_HASWELL_ULT_M_GT1 || \ - (devid) == PCI_CHIP_HASWELL_ULT_S_GT1 || \ - (devid) == PCI_CHIP_HASWELL_ULT_B_GT1 || \ - (devid) == PCI_CHIP_HASWELL_ULT_E_GT1 || \ - (devid) == PCI_CHIP_HASWELL_CRW_GT1 || \ - (devid) == PCI_CHIP_HASWELL_CRW_M_GT1 || \ - (devid) == PCI_CHIP_HASWELL_CRW_S_GT1 || \ - (devid) == PCI_CHIP_HASWELL_CRW_B_GT1 || \ - (devid) == PCI_CHIP_HASWELL_CRW_E_GT1) -#define IS_HSW_GT2(devid) ((devid) == PCI_CHIP_HASWELL_GT2 || \ - (devid) == PCI_CHIP_HASWELL_M_GT2 || \ - (devid) == PCI_CHIP_HASWELL_S_GT2 || \ - (devid) == PCI_CHIP_HASWELL_B_GT2 || \ - (devid) == PCI_CHIP_HASWELL_E_GT2 || \ - (devid) == PCI_CHIP_HASWELL_SDV_GT2 || \ - (devid) == PCI_CHIP_HASWELL_SDV_M_GT2 || \ - (devid) == PCI_CHIP_HASWELL_SDV_S_GT2 || \ - (devid) == PCI_CHIP_HASWELL_SDV_B_GT2 || \ - (devid) == PCI_CHIP_HASWELL_SDV_E_GT2 || \ - (devid) == PCI_CHIP_HASWELL_ULT_GT2 || \ - (devid) == PCI_CHIP_HASWELL_ULT_M_GT2 || \ - (devid) == PCI_CHIP_HASWELL_ULT_S_GT2 || \ - (devid) == PCI_CHIP_HASWELL_ULT_B_GT2 || \ - (devid) == PCI_CHIP_HASWELL_ULT_E_GT2 || \ - (devid) == PCI_CHIP_HASWELL_CRW_GT2 || \ - (devid) == PCI_CHIP_HASWELL_CRW_M_GT2 || \ - (devid) == PCI_CHIP_HASWELL_CRW_S_GT2 || \ - (devid) == PCI_CHIP_HASWELL_CRW_B_GT2 || \ - (devid) == PCI_CHIP_HASWELL_CRW_E_GT2) -#define IS_HSW_GT3(devid) ((devid) == PCI_CHIP_HASWELL_GT3 || \ - (devid) == PCI_CHIP_HASWELL_M_GT3 || \ - (devid) == PCI_CHIP_HASWELL_S_GT3 || \ - (devid) == PCI_CHIP_HASWELL_B_GT3 || \ - (devid) == PCI_CHIP_HASWELL_E_GT3 || \ - (devid) == PCI_CHIP_HASWELL_SDV_GT3 || \ - (devid) == PCI_CHIP_HASWELL_SDV_M_GT3 || \ - (devid) == PCI_CHIP_HASWELL_SDV_S_GT3 || \ - (devid) == PCI_CHIP_HASWELL_SDV_B_GT3 || \ - (devid) == PCI_CHIP_HASWELL_SDV_E_GT3 || \ - (devid) == PCI_CHIP_HASWELL_ULT_GT3 || \ - (devid) == PCI_CHIP_HASWELL_ULT_M_GT3 || \ - (devid) == PCI_CHIP_HASWELL_ULT_S_GT3 || \ - (devid) == PCI_CHIP_HASWELL_ULT_B_GT3 || \ - (devid) == PCI_CHIP_HASWELL_ULT_E_GT3 || \ - (devid) == PCI_CHIP_HASWELL_CRW_GT3 || \ - (devid) == PCI_CHIP_HASWELL_CRW_M_GT3 || \ - (devid) == PCI_CHIP_HASWELL_CRW_S_GT3 || \ - (devid) == PCI_CHIP_HASWELL_CRW_B_GT3 || \ - (devid) == PCI_CHIP_HASWELL_CRW_E_GT3) - -#define IS_HASWELL(devid) (IS_HSW_GT1(devid) || \ - IS_HSW_GT2(devid) || \ - IS_HSW_GT3(devid)) - -#define IS_BROADWELL(devid) (((devid & 0xff00) != 0x1600) ? 0 : \ - (((devid & 0x00f0) >> 4) > 3) ? 0 : \ - ((devid & 0x000f) == BDW_SPARE) ? 1 : \ - ((devid & 0x000f) == BDW_ULT) ? 1 : \ - ((devid & 0x000f) == BDW_IRIS) ? 1 : \ - ((devid & 0x000f) == BDW_SERVER) ? 1 : \ - ((devid & 0x000f) == BDW_WORKSTATION) ? 1 : \ - ((devid & 0x000f) == BDW_ULX) ? 1 : 0) - -#define IS_CHERRYVIEW(devid) ((devid) == PCI_CHIP_CHERRYVIEW_0 || \ - (devid) == PCI_CHIP_CHERRYVIEW_1 || \ - (devid) == PCI_CHIP_CHERRYVIEW_2 || \ - (devid) == PCI_CHIP_CHERRYVIEW_3) - -#define IS_GEN8(devid) (IS_BROADWELL(devid) || \ - IS_CHERRYVIEW(devid)) - -#define IS_SKL_GT1(devid) ((devid) == PCI_CHIP_SKYLAKE_DT_GT1 || \ - (devid) == PCI_CHIP_SKYLAKE_ULT_GT1 || \ - (devid) == PCI_CHIP_SKYLAKE_SRV_GT1 || \ - (devid) == PCI_CHIP_SKYLAKE_H_GT1 || \ - (devid) == PCI_CHIP_SKYLAKE_ULX_GT1) - -#define IS_SKL_GT2(devid) ((devid) == PCI_CHIP_SKYLAKE_DT_GT2 || \ - (devid) == PCI_CHIP_SKYLAKE_FUSED0_GT2 || \ - (devid) == PCI_CHIP_SKYLAKE_FUSED1_GT2 || \ - (devid) == PCI_CHIP_SKYLAKE_ULT_GT2 || \ - (devid) == PCI_CHIP_SKYLAKE_FUSED2_GT2 || \ - (devid) == PCI_CHIP_SKYLAKE_SRV_GT2 || \ - (devid) == PCI_CHIP_SKYLAKE_HALO_GT2 || \ - (devid) == PCI_CHIP_SKYLAKE_WKS_GT2 || \ - (devid) == PCI_CHIP_SKYLAKE_ULX_GT2 || \ - (devid) == PCI_CHIP_SKYLAKE_MOBILE_GT2) - -#define IS_SKL_GT3(devid) ((devid) == PCI_CHIP_SKYLAKE_ULT_GT3_0 || \ - (devid) == PCI_CHIP_SKYLAKE_ULT_GT3_1 || \ - (devid) == PCI_CHIP_SKYLAKE_ULT_GT3_2 || \ - (devid) == PCI_CHIP_SKYLAKE_HALO_GT3 || \ - (devid) == PCI_CHIP_SKYLAKE_SRV_GT3) - -#define IS_SKL_GT4(devid) ((devid) == PCI_CHIP_SKYLAKE_SRV_GT4 || \ - (devid) == PCI_CHIP_SKYLAKE_DT_GT4 || \ - (devid) == PCI_CHIP_SKYLAKE_SRV_GT4X || \ - (devid) == PCI_CHIP_SKYLAKE_H_GT4 || \ - (devid) == PCI_CHIP_SKYLAKE_WKS_GT4) - -#define IS_KBL_GT1(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT1_5 || \ - (devid) == PCI_CHIP_KABYLAKE_ULX_GT1_5 || \ - (devid) == PCI_CHIP_KABYLAKE_DT_GT1_5 || \ - (devid) == PCI_CHIP_KABYLAKE_ULT_GT1 || \ - (devid) == PCI_CHIP_KABYLAKE_ULX_GT1 || \ - (devid) == PCI_CHIP_KABYLAKE_DT_GT1 || \ - (devid) == PCI_CHIP_KABYLAKE_HALO_GT1_0 || \ - (devid) == PCI_CHIP_KABYLAKE_HALO_GT1_1 || \ - (devid) == PCI_CHIP_KABYLAKE_SRV_GT1) - -#define IS_KBL_GT2(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT2 || \ - (devid) == PCI_CHIP_KABYLAKE_ULT_GT2F || \ - (devid) == PCI_CHIP_KABYLAKE_ULX_GT2 || \ - (devid) == PCI_CHIP_KABYLAKE_DT_GT2 || \ - (devid) == PCI_CHIP_KABYLAKE_HALO_GT2 || \ - (devid) == PCI_CHIP_KABYLAKE_SRV_GT2 || \ - (devid) == PCI_CHIP_KABYLAKE_WKS_GT2) - -#define IS_KBL_GT3(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT3_0 || \ - (devid) == PCI_CHIP_KABYLAKE_ULT_GT3_1 || \ - (devid) == PCI_CHIP_KABYLAKE_ULT_GT3_2) - -#define IS_KBL_GT4(devid) ((devid) == PCI_CHIP_KABYLAKE_HALO_GT4) - -#define IS_KABYLAKE(devid) (IS_KBL_GT1(devid) || \ - IS_KBL_GT2(devid) || \ - IS_KBL_GT3(devid) || \ - IS_KBL_GT4(devid)) - -#define IS_SKYLAKE(devid) (IS_SKL_GT1(devid) || \ - IS_SKL_GT2(devid) || \ - IS_SKL_GT3(devid) || \ - IS_SKL_GT4(devid)) - -#define IS_BROXTON(devid) ((devid) == PCI_CHIP_BROXTON_0 || \ - (devid) == PCI_CHIP_BROXTON_1 || \ - (devid) == PCI_CHIP_BROXTON_2 || \ - (devid) == PCI_CHIP_BROXTON_3 || \ - (devid) == PCI_CHIP_BROXTON_4) - -#define IS_GEMINILAKE(devid) ((devid) == PCI_CHIP_GLK || \ - (devid) == PCI_CHIP_GLK_2X6) - -#define IS_GEN9(devid) (IS_SKYLAKE(devid) || \ - IS_BROXTON(devid) || \ - IS_KABYLAKE(devid) || \ - IS_GEMINILAKE(devid)) - -#define IS_9XX(dev) (IS_GEN3(dev) || \ - IS_GEN4(dev) || \ - IS_GEN5(dev) || \ - IS_GEN6(dev) || \ - IS_GEN7(dev) || \ - IS_GEN8(dev) || \ - IS_GEN9(dev)) - - -#endif /* _INTEL_CHIPSET_H */ diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c index 536e4c4153c..d009543e5d8 100644 --- a/src/mesa/drivers/dri/i965/intel_screen.c +++ b/src/mesa/drivers/dri/i965/intel_screen.c @@ -1272,9 +1272,11 @@ intel_init_bufmgr(struct intel_screen *screen) { __DRIscreen *dri_screen = screen->driScrnPriv; - screen->no_hw = getenv("INTEL_NO_HW") != NULL; + if (getenv("INTEL_NO_HW") != NULL) + screen->no_hw = true; - screen->bufmgr = drm_bacon_bufmgr_gem_init(dri_screen->fd, BATCH_SZ); + screen->bufmgr = drm_bacon_bufmgr_gem_init(&screen->devinfo, + dri_screen->fd, BATCH_SZ); if (screen->bufmgr == NULL) { fprintf(stderr, "[%s:%u] Error initializing buffer manager.\n", __func__, __LINE__); @@ -1727,6 +1729,53 @@ shader_perf_log_mesa(void *data, const char *fmt, ...) va_end(args); } +static int +parse_devid_override(const char *devid_override) +{ + static const struct { + const char *name; + int pci_id; + } name_map[] = { + { "brw", 0x2a02 }, + { "g4x", 0x2a42 }, + { "ilk", 0x0042 }, + { "snb", 0x0126 }, + { "ivb", 0x016a }, + { "hsw", 0x0d2e }, + { "byt", 0x0f33 }, + { "bdw", 0x162e }, + { "skl", 0x1912 }, + { "kbl", 0x5912 }, + }; + + for (unsigned i = 0; i < ARRAY_SIZE(name_map); i++) { + if (!strcmp(name_map[i].name, devid_override)) + return name_map[i].pci_id; + } + + return strtod(devid_override, NULL); +} + +/** + * Get the PCI ID for the device. This can be overridden by setting the + * INTEL_DEVID_OVERRIDE environment variable to the desired ID. + * + * Returns -1 on ioctl failure. + */ +static int +get_pci_device_id(struct intel_screen *screen) +{ + if (geteuid() == getuid()) { + char *devid_override = getenv("INTEL_DEVID_OVERRIDE"); + if (devid_override) { + screen->no_hw = true; + return parse_devid_override(devid_override); + } + } + + return intel_get_integer(screen, I915_PARAM_CHIPSET_ID); +} + /** * This is the driver specific part of the createNewScreen entry point. * Called when using DRI2. @@ -1759,13 +1808,14 @@ __DRIconfig **intelInitScreen2(__DRIscreen *dri_screen) screen->driScrnPriv = dri_screen; dri_screen->driverPrivate = (void *) screen; - if (!intel_init_bufmgr(screen)) - return NULL; + screen->deviceID = get_pci_device_id(screen); - screen->deviceID = drm_bacon_bufmgr_gem_get_devid(screen->bufmgr); if (!gen_get_device_info(screen->deviceID, &screen->devinfo)) return NULL; + if (!intel_init_bufmgr(screen)) + return NULL; + const struct gen_device_info *devinfo = &screen->devinfo; brw_process_intel_debug_variable();