From: lkcl <lkcl@web>
Date: Mon, 20 Sep 2021 12:18:11 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~49
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1dc7f35bbf40212b986be3b0951261002dc2b758;p=libreriscv.git

---

diff --git a/lkcl.mdwn b/lkcl.mdwn
index bdf05cc90..695ecc4f3 100644
--- a/lkcl.mdwn
+++ b/lkcl.mdwn
@@ -47,7 +47,6 @@ move things along from one stage to the next
  - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
  - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
  - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
- - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
  - <https://bugs.libre-soc.org/show_bug.cgi?id=427> LD/ST cache-inhibit
    - EUR 200
  - <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API 
@@ -63,6 +62,7 @@ move things along from one stage to the next
  - <https://bugs.libre-soc.org/show_bug.cgi?id=639> SVP64 test documentation 
 
 ## Completed but not yet submitted:
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
  - <https://bugs.libre-soc.org/show_bug.cgi?id=425> div errors
  - <https://bugs.libre-soc.org/show_bug.cgi?id=432> mul overflow incorrect
  - <https://bugs.libre-soc.org/show_bug.cgi?id=604> ISACaller RADIX MMU