From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 25 May 2020 23:39:16 +0000 (-0700)
Subject: tests: add ecp5 latch testcase with -abc9
X-Git-Tag: working-ls180~512^2~3
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1dce798dc5050745490600c09c873d821548f4f7;p=yosys.git

tests: add ecp5 latch testcase with -abc9
---

diff --git a/tests/arch/ecp5/latches_abc9.ys b/tests/arch/ecp5/latches_abc9.ys
new file mode 100644
index 000000000..ca3182254
--- /dev/null
+++ b/tests/arch/ecp5/latches_abc9.ys
@@ -0,0 +1,16 @@
+read_verilog <<EOT
+module top(input e, d, output q);
+reg l;
+always @*
+    if (e)
+        l = ~d;
+assign q = ~l;
+endmodule
+EOT
+proc
+design -save gold
+
+# Can't run any sort of equivalence check because latches are blown to LUTs
+synth_ecp5 -abc9
+select -assert-count 2 t:LUT4
+select -assert-none t:LUT4 %% t:* %D