From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 25 Sep 2018 05:47:30 +0000 (+0100)
Subject: add decode.h header to sv.h
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1dfc22c8fe1bfb3387195df4a0509bbd35c33678;p=riscv-isa-sim.git

add decode.h header to sv.h
---

diff --git a/riscv/sv.h b/riscv/sv.h
index 7b98c92..cd2f8fb 100644
--- a/riscv/sv.h
+++ b/riscv/sv.h
@@ -3,6 +3,8 @@
 #ifndef _RISCV_SIMPLE_V_H
 #define _RISCV_SIMPLE_V_H
 
+#include "decode.h"
+
 // this table is for the CSRs (4? for RV32E, 16 for other types)
 // it's a CAM that's used to generate 2 tables (below)
 // just as in RV, writing to entries in this CAM *clears*