From: Jean THOMAS <git0@pub.jeanthomas.me>
Date: Mon, 13 Jul 2020 11:06:58 +0000 (+0200)
Subject: Fix gearing and UART speed
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1e0b9f6e006686c192314d72532680fe012ad6ff;p=gram.git

Fix gearing and UART speed
---

diff --git a/gram/simulation/simsoc.py b/gram/simulation/simsoc.py
index 5f813ef..e008935 100644
--- a/gram/simulation/simsoc.py
+++ b/gram/simulation/simsoc.py
@@ -26,13 +26,13 @@ class DDR3SoC(SoC, Elaboratable):
         self._decoder = wishbone.Decoder(addr_width=30, data_width=32, granularity=8,
                                          features={"cti", "bte"})
 
-        self.ub = UARTBridge(divisor=868, pins=platform.request("uart", 0))
+        self.ub = UARTBridge(divisor=217, pins=platform.request("uart", 0))
         self._arbiter.add(self.ub.bus)
 
         self.ddrphy = DomainRenamer("dramsync")(ECP5DDRPHY(platform.request("ddr3", 0, dir={"dq":"-", "dqs":"-"})))
         self._decoder.add(self.ddrphy.bus, addr=ddrphy_addr)
 
-        ddrmodule = MT41K256M16(clk_freq, "1:4")
+        ddrmodule = MT41K256M16(clk_freq, "1:2")
 
         self.dramcore = DomainRenamer("dramsync")(gramCore(
             phy=self.ddrphy,
diff --git a/gram/simulation/simsoctb.v b/gram/simulation/simsoctb.v
index 0473678..f8e4199 100644
--- a/gram/simulation/simsoctb.v
+++ b/gram/simulation/simsoctb.v
@@ -113,7 +113,7 @@ module simsoctb;
     begin
       uart_rx <= 1'b1;
       $display("[%t] Starting POR",$time);
-      #700000; // POR is ~700us
+      #100; // POR is ~700us
       $display("[%t] POR complete",$time);
 
       // Software control
@@ -124,7 +124,7 @@ module simsoctb;
       wishbone_write(32'h00009000 >> 2, 8'h0C); // DFII_CONTROL_ODT|DFII_CONTROL_RESET_N
       #500000;
       wishbone_write(32'h00009000 >> 2, 8'h0E); // DFII_CONTROL_ODT|DFII_CONTROL_RESET_N|DFI_CONTROL_CKE
-      #500000;
+      #100000;
 
       // Set MR2
       wishbone_write(32'h0000900c >> 2, 32'h200); // p0 address
@@ -162,6 +162,9 @@ module simsoctb;
       wishbone_write(32'h00009000 >> 2, 8'h01); // DFII_CONTROL_SEL
       #2000;
 
+      wishbone_read(32'h10000000 >> 2, tmp);
+      #2000;
+
       // Write
       wishbone_write(32'h10000000 >> 2, 32'h12345678);
       #10000;
@@ -212,14 +215,14 @@ module simsoctb;
 
     begin
       uart_rx <= 1'b0;
-      #8680;
+      #2170;
       for (i = 0; i < 8; i = i + 1)
         begin
           uart_rx <= data[i];
-          #8680;
+          #2170;
         end
       uart_rx <= 1'b1;
-      #8680;
+      #2170;
     end
   endtask
 
@@ -235,10 +238,10 @@ module simsoctb;
 
       for (i = 0; i < 8; i = i+1)
         begin
-          #8680 data[i] <= uart_tx;
+          #2170 data[i] <= uart_tx;
         end
 
-      #8680;
+      #2170;
     end
   endtask
 endmodule