From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 13 Apr 2015 12:47:44 +0000 (+0200)
Subject: liteusb: more pep8 (when convenient), should be almost OK
X-Git-Tag: 24jan2021_ls180~2342
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1e1f7ce30e46267033bf77295fbbbd6ee388859a;p=litex.git

liteusb: more pep8 (when convenient), should be almost OK
---

diff --git a/misoclib/com/liteusb/common.py b/misoclib/com/liteusb/common.py
index 2f6f9772..eaa9f162 100644
--- a/misoclib/com/liteusb/common.py
+++ b/misoclib/com/liteusb/common.py
@@ -1,3 +1,5 @@
+import random
+
 from migen.fhdl.std import *
 from migen.genlib.fsm import *
 from migen.actorlib.fifo import *
@@ -38,12 +40,10 @@ class LiteUSBTimeout(Module):
             )
         self.comb += self.done.eq(cnt == cnt_max)
 
+
 #
 # TB
 #
-import random
-
-
 def randn(max_n):
     return random.randint(0, max_n-1)
 
diff --git a/misoclib/com/liteusb/core/crc.py b/misoclib/com/liteusb/core/crc.py
index 83aab313..bfea13f6 100644
--- a/misoclib/com/liteusb/core/crc.py
+++ b/misoclib/com/liteusb/core/crc.py
@@ -103,6 +103,7 @@ class CRC32(Module):
     polynom = 0x04C11DB7
     init = 2**width-1
     check = 0xC704DD7B
+
     def __init__(self, dat_width):
         self.d = Signal(dat_width)
         self.value = Signal(self.width)
diff --git a/misoclib/com/liteusb/core/depacketizer.py b/misoclib/com/liteusb/core/depacketizer.py
index 77a8ad9c..aa308b01 100644
--- a/misoclib/com/liteusb/core/depacketizer.py
+++ b/misoclib/com/liteusb/core/depacketizer.py
@@ -77,7 +77,9 @@ class LiteUSBDepacketizer(Module):
             source.eop.eq(eop),
             source.d.eq(sink.d),
             sink.ack.eq(source.ack),
-            If((eop & sink.stb & source.ack) | self.timeout.done, NextState("WAIT_SOP"))
+            If((eop & sink.stb & source.ack) | self.timeout.done,
+                NextState("WAIT_SOP")
+            )
         )
 
         self.sync += \
@@ -94,7 +96,8 @@ class LiteUSBDepacketizer(Module):
 #
 src_data = [
     0x5A, 0xA5, 0x5A, 0xA5, 0x01, 0x00, 0x00, 0x00, 0x04, 0x00, 0x01, 0x02, 0x03,
-    0x5A, 0xA5, 0x5A, 0xA5, 0x12, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
+    0x5A, 0xA5, 0x5A, 0xA5, 0x12, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01, 0x02, 0x03,
+    0x04, 0x05, 0x06, 0x07,
 ]*4
 
 
diff --git a/misoclib/com/liteusb/frontend/uart.py b/misoclib/com/liteusb/frontend/uart.py
index 1147fa68..68a032ec 100644
--- a/misoclib/com/liteusb/frontend/uart.py
+++ b/misoclib/com/liteusb/frontend/uart.py
@@ -24,7 +24,7 @@ class LiteUSBUART(Module, AutoCSR):
 
         # TX
         tx_start = self._rxtx.re
-        tx_done  = self.ev.tx.trigger
+        tx_done = self.ev.tx.trigger
 
         self.sync += \
             If(tx_start,
diff --git a/misoclib/com/liteusb/phy/ft2232h.py b/misoclib/com/liteusb/phy/ft2232h.py
index d8e70dd6..349dc608 100644
--- a/misoclib/com/liteusb/phy/ft2232h.py
+++ b/misoclib/com/liteusb/phy/ft2232h.py
@@ -68,7 +68,7 @@ class FT2232HPHY(Module):
         read_time_en, max_read_time = anti_starvation(read_time)
         write_time_en, max_write_time = anti_starvation(write_time)
 
-        data_w_accepted  = Signal(reset=1)
+        data_w_accepted = Signal(reset=1)
 
         fsm = FSM()
         self.submodules += RenameClockDomains(fsm, {"sys": "ftdi"})
@@ -97,8 +97,8 @@ class FT2232HPHY(Module):
         # Read / Write Actions
         #
 
-        data_w  = Signal(dw)
-        data_r  = Signal(dw)
+        data_w = Signal(dw)
+        data_r = Signal(dw)
         data_oe = Signal()
 
         if hasattr(pads, "oe_n"):
@@ -256,7 +256,7 @@ class UserModel(Module, RandRun):
 
 LENGTH = 512
 model_rd_data = [i%256 for i in range(LENGTH)][::-1]
-user_wr_data  = [i%256 for i in range(LENGTH)]
+user_wr_data = [i%256 for i in range(LENGTH)]
 
 
 class TB(Module):