From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 20 May 2016 14:58:02 +0000 (+0200)
Subject: Improvements and fixes in autotest.sh script and test_autotb
X-Git-Tag: yosys-0.7~216
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1e227caf720bc5870ea9244e6b5657cf9c9717ab;p=yosys.git

Improvements and fixes in autotest.sh script and test_autotb
---

diff --git a/passes/tests/test_autotb.cc b/passes/tests/test_autotb.cc
index cf01074ea..59de111c2 100644
--- a/passes/tests/test_autotb.cc
+++ b/passes/tests/test_autotb.cc
@@ -73,8 +73,8 @@ static std::string idy(std::string str1, std::string str2 = std::string(), std::
 
 static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter)
 {
-	f << stringf("`ifndef dmp_name\n");
-	f << stringf("\t`define dmp_name \"not_defined.dmp\"\n");
+	f << stringf("`ifndef outfile\n");
+	f << stringf("\t`define outfile \"/dev/stdout\"\n");
 	f << stringf("`endif\n");
 
 	f << stringf("module testbench;\n\n");
@@ -301,7 +301,7 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter)
 	f << stringf("initial begin\n");
 	f << stringf("\t// $dumpfile(\"testbench.vcd\");\n");
 	f << stringf("\t// $dumpvars(0, testbench);\n");
-	f << stringf("\tfile = $fopen(`dmp_name);\n");
+	f << stringf("\tfile = $fopen(`outfile);\n");
 	for (auto it = design->modules_.begin(); it != design->modules_.end(); ++it)
 		if (!it->second->get_bool_attribute("\\gentb_skip"))
 			f << stringf("\t%s;\n", idy(it->first.str(), "test").c_str());
diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh
index feaadb1a1..bc43fb885 100755
--- a/tests/tools/autotest.sh
+++ b/tests/tools/autotest.sh
@@ -16,7 +16,7 @@ toolsdir="$(cd $(dirname $0); pwd)"
 warn_iverilog_git=false
 
 if [ ! -f $toolsdir/cmp_tbdata -o $toolsdir/cmp_tbdata.c -nt $toolsdir/cmp_tbdata ]; then
-	( set -ex;  ${CC:-gcc} -Wall -o $toolsdir/cmp_tbdata $toolsdir/cmp_tbdata.c; ) || exit 1
+	( set -ex; ${CC:-gcc} -Wall -o $toolsdir/cmp_tbdata $toolsdir/cmp_tbdata.c; ) || exit 1
 fi
 
 while getopts xmGl:wkjvref:s:p:n: opt; do
@@ -65,18 +65,18 @@ compile_and_run() {
 	if $use_modelsim; then
 		altver=$( ls -v /opt/altera/ | grep '^[0-9]' | tail -n1; )
 		/opt/altera/$altver/modelsim_ase/bin/vlib work
-		/opt/altera/$altver/modelsim_ase/bin/vlog +define+dmp_name=\"$output\" "$@"
+		/opt/altera/$altver/modelsim_ase/bin/vlog +define+outfile=\"$output\" "$@"
 		/opt/altera/$altver/modelsim_ase/bin/vsim -c -do 'run -all; exit;' testbench
 	elif $use_xsim; then
 		(
 			set +x
 			files=( "$@" )
 			xilver=$( ls -v /opt/Xilinx/Vivado/ | grep '^[0-9]' | tail -n1; )
-			/opt/Xilinx/Vivado/$xilver/bin/xvlog "${files[@]}"
-			/opt/Xilinx/Vivado/$xilver/bin/xelab -R work.testbench | grep '#OUT#' > "$output"
+			/opt/Xilinx/Vivado/$xilver/bin/xvlog -d outfile=\"$output\" "${files[@]}"
+			/opt/Xilinx/Vivado/$xilver/bin/xelab -R work.testbench
 		)
 	else
-		iverilog  -Ddmp_name=\"$output\" -s testbench -o "$exe" "$@" 
+		iverilog -Doutfile=\"$output\" -s testbench -o "$exe" "$@"
 		vvp -n "$exe"
 	fi
 }
@@ -116,7 +116,7 @@ do
 		fi
 		if $genvcd; then sed -i 's,// \$dump,$dump,g' ${bn}_tb.v; fi
 		create_ref $fn ${bn}_ref
-		compile_and_run  ${bn}_tb_ref ${bn}_out_ref ${bn}_tb.v ${bn}_ref.v $libs
+		compile_and_run ${bn}_tb_ref ${bn}_out_ref ${bn}_tb.v ${bn}_ref.v $libs
 		if $genvcd; then mv testbench.vcd ${bn}_ref.vcd; fi
 
 		test_count=0