From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 1 Feb 2014 12:04:49 +0000 (+0100)
Subject: Added note about SystemVerilog assert statement to README
X-Git-Tag: yosys-0.2.0~126
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1e2440e7ed6979bdee2f80116d6c3a429b604e25;p=yosys.git

Added note about SystemVerilog assert statement to README
---

diff --git a/README b/README
index 307f594b4..f0c9bc747 100644
--- a/README
+++ b/README
@@ -270,6 +270,11 @@ Verilog Attributes and non-standard features
   for everything that comes after the {* ... *} statement. (Reset
   by adding an empty {* *} statement.)
 
+- The "assert" statement from SystemVerilog is supported in its most basic
+  form. In module context: "assert property (<expression>);" and within an
+  always block: "assert(<expression>);". It is transformed to a $assert cell
+  that is supported by the "sat" and "write_btor" commands.
+
 
 Workarounds for known build problems
 ====================================