From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 2 May 2019 17:22:55 +0000 (+0100)
Subject: get test_mul.py operational
X-Git-Tag: ls180-24jan2020~1065
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1e3a15f07bf03874164403669ff7dac3eab88a29;p=ieee754fpu.git

get test_mul.py operational
---

diff --git a/src/ieee754/fpmul/fmul.py b/src/ieee754/fpmul/fmul.py
index 3ad9e539..e7454384 100644
--- a/src/ieee754/fpmul/fmul.py
+++ b/src/ieee754/fpmul/fmul.py
@@ -1,9 +1,10 @@
 from nmigen import Module, Signal, Cat, Mux, Array, Const
 from nmigen.cli import main, verilog
 
-from ieee754.fpcommon.fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPState
-from fpcommon.getop import FPGetOp
-from nmutil.singlepipe import eq
+from ieee754.fpcommon.fpbase import (FPNumIn, FPNumOut, FPOpIn,
+                                     FPOpOut, Overflow, FPBase, FPState)
+from ieee754.fpcommon.getop import FPGetOp
+from nmutil.nmoperator import eq
 
 
 class FPMUL(FPBase):
@@ -12,9 +13,9 @@ class FPMUL(FPBase):
         FPBase.__init__(self)
         self.width = width
 
-        self.in_a  = FPOp(width)
-        self.in_b  = FPOp(width)
-        self.out_z = FPOp(width)
+        self.in_a  = FPOpIn(width)
+        self.in_b  = FPOpIn(width)
+        self.out_z = FPOpOut(width)
 
         self.states = []
 
diff --git a/src/ieee754/fpmul/test/test_mul.py b/src/ieee754/fpmul/test/test_mul.py
index 21d82528..a1cf8e55 100644
--- a/src/ieee754/fpmul/test/test_mul.py
+++ b/src/ieee754/fpmul/test/test_mul.py
@@ -6,15 +6,15 @@ from operator import mul
 from nmigen import Module, Signal
 from nmigen.compat.sim import run_simulation
 
-from fmul import FPMUL
+from ieee754.fpmul.fmul import FPMUL
 
-from unit_test_single import (get_mantissa, get_exponent, get_sign, is_nan,
+from ieee754.fpcommon.test.unit_test_single import (get_mantissa, get_exponent, get_sign, is_nan,
                                 is_inf, is_pos_inf, is_neg_inf,
                                 match, get_case, check_case, run_test,
                                 run_edge_cases, run_corner_cases)
 
 
-def testbench(dut):
+def tbench(dut):
     yield from check_case(dut, 0x40000000, 0x40000000, 0x40800000)
     yield from check_case(dut, 0x41400000, 0x40A00000, 0x42700000)
 
@@ -33,7 +33,9 @@ def testbench(dut):
     yield from run_edge_cases(dut, count, mul, get_case)
 
 
-if __name__ == '__main__':
+def test1():
     dut = FPMUL(width=32)
-    run_simulation(dut, testbench(dut), vcd_name="test_mul.vcd")
+    run_simulation(dut, tbench(dut), vcd_name="test_mul.vcd")
 
+if __name__ == '__main__':
+    test1()