From: Dmitry Selyutin <dmitry.selyutin@3mdeb.com>
Date: Fri, 3 Sep 2021 20:29:00 +0000 (+0000)
Subject: test_runner: support custom pdecode2 instances
X-Git-Tag: xlen-bcd~14
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1e3aa045747eb77bc90139be0bd924dbf45a7cb5;p=openpower-isa.git

test_runner: support custom pdecode2 instances
---

diff --git a/src/openpower/decoder/isa/test_runner.py b/src/openpower/decoder/isa/test_runner.py
index 7cfc6304..eac12954 100644
--- a/src/openpower/decoder/isa/test_runner.py
+++ b/src/openpower/decoder/isa/test_runner.py
@@ -89,20 +89,23 @@ class ISATestRunner(FHDLTestCase):
 
 def run_tst(generator, initial_regs, initial_sprs=None, svstate=0, mmu=False,
                                      initial_cr=0, mem=None,
-                                     initial_fprs=None):
+                                     initial_fprs=None,
+                                     pdecode2=None):
     if initial_sprs is None:
         initial_sprs = {}
     m = Module()
     comb = m.d.comb
     instruction = Signal(32)
 
-    pdecode = create_pdecode(include_fp=initial_fprs is not None)
+    if pdecode2 is None:
+        pdecode = create_pdecode(include_fp=initial_fprs is not None)
+        pdecode2 = PowerDecode2(pdecode)
+    m.submodules.pdecode2 = pdecode2
 
     gen = list(generator.generate_instructions())
     insncode = generator.assembly.splitlines()
     instructions = list(zip(gen, insncode))
 
-    m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
     simulator = ISA(pdecode2, initial_regs, initial_sprs, initial_cr,
                     initial_insns=gen, respect_pc=True,
                     initial_svstate=svstate,