From: lkcl <lkcl@web>
Date: Tue, 6 Jun 2023 14:03:47 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1e3dbc4e355265f6c258e1382c0b7b55405253bd;p=libreriscv.git

---

diff --git a/openpower/sv/compliancy_levels.mdwn b/openpower/sv/compliancy_levels.mdwn
index 577cde76e..4d6e08a5a 100644
--- a/openpower/sv/compliancy_levels.mdwn
+++ b/openpower/sv/compliancy_levels.mdwn
@@ -29,10 +29,9 @@ Summary of Compliancy Levels, each Level includes all lower levels:
 
 * **Zero-Level**: Simple-V is not implemented (at all) in hardware. This
   Level is required to be listed because all capabilities of Simple-V
-  must be Soft-emulatable.
-* **Ultra-embedded**: `setvl` instruction and context-switching of SVSTATE
-  to/from SVSRR1. Register Files as Standard Power ISA. `scalar identity`
-  implemented.
+  must be Soft-emulatable by way of Illegal Instruction Traps.
+* **Ultra-embedded**: `setvl` instruction. Register Files as Standard Power
+  ISA. `scalar identity behaviour` implemented.
 * **Embedded**: `svstep` instruction,
   and support for Hardware for-looping
   in both Horizontal-First and Vertical-First Mode as well as Predication