From: Robert Ou <rqou@robertou.com>
Date: Tue, 1 Aug 2017 18:58:01 +0000 (-0700)
Subject: coolrunner2: Add FFs with clock enable to cells_sim.v
X-Git-Tag: yosys-0.8~349^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1e3ffd57cbfce0ec6f1bdd4f2dd20d18e0855c57;p=yosys.git

coolrunner2: Add FFs with clock enable to cells_sim.v
---

diff --git a/techlibs/coolrunner2/cells_sim.v b/techlibs/coolrunner2/cells_sim.v
index e08ee5f9b..d8dca1922 100644
--- a/techlibs/coolrunner2/cells_sim.v
+++ b/techlibs/coolrunner2/cells_sim.v
@@ -244,3 +244,63 @@ module FTDCP (C, PRE, CLR, T, Q);
 
     assign Q = Q_;
 endmodule
+
+module FDCPE (C, PRE, CLR, D, Q, CE);
+    parameter INIT = 0;
+
+    input C, PRE, CLR, D, CE;
+    output reg Q;
+
+    initial begin
+        Q <= INIT;
+    end
+
+    always @(posedge C, posedge PRE, posedge CLR) begin
+        if (CLR == 1)
+            Q <= 0;
+        else if (PRE == 1)
+            Q <= 1;
+        else if (CE == 1)
+            Q <= D;
+    end
+endmodule
+
+module FDCPE_N (C, PRE, CLR, D, Q, CE);
+    parameter INIT = 0;
+
+    input C, PRE, CLR, D, CE;
+    output reg Q;
+
+    initial begin
+        Q <= INIT;
+    end
+
+    always @(negedge C, posedge PRE, posedge CLR) begin
+        if (CLR == 1)
+            Q <= 0;
+        else if (PRE == 1)
+            Q <= 1;
+        else if (CE == 1)
+            Q <= D;
+    end
+endmodule
+
+module FDDCPE (C, PRE, CLR, D, Q, CE);
+    parameter INIT = 0;
+
+    input C, PRE, CLR, D, CE;
+    output reg Q;
+
+    initial begin
+        Q <= INIT;
+    end
+
+    always @(posedge C, negedge C, posedge PRE, posedge CLR) begin
+        if (CLR == 1)
+            Q <= 0;
+        else if (PRE == 1)
+            Q <= 1;
+        else if (CE == 1)
+            Q <= D;
+    end
+endmodule