From: Jakub Jelinek Date: Sat, 30 Dec 2017 16:01:50 +0000 (+0100) Subject: sse.md (vgf2p8affineinvqb_, [...]): Formatting fixes. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1e4423dbb50bcafd41a1246602e4222d8562eb93;p=gcc.git sse.md (vgf2p8affineinvqb_, [...]): Formatting fixes. * config/i386/sse.md (vgf2p8affineinvqb_, vgf2p8affineqb_, vgf2p8mulb_, vpshrd_, vpshld_, vpshrdv_, vpshrdv__mask, vpshrdv__maskz, vpshrdv__maskz_1, vpshldv_, vpshldv__mask, vpshldv__maskz, vpshldv__maskz_1, vpdpbusd_, vpdpbusd__mask, vpdpbusd__maskz, vpdpbusd__maskz_1, vpdpbusds_, vpdpbusds__mask, vpdpbusds__maskz, vpdpbusds__maskz_1, vpdpwssd_, vpdpwssd__mask, vpdpwssd__maskz, vpdpwssd__maskz_1, vpdpwssds_, vpdpwssds__mask, vpdpwssds__maskz, vpdpwssds__maskz_1, vaesdec_, vaesdeclast_, vaesenc_, vpclmulqdq_, avx512vl_vpshufbitqmb): Formatting fixes. From-SVN: r256044 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c3a0ef322d8..18a92a98055 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,20 @@ +2017-12-30 Jakub Jelinek + + * config/i386/sse.md (vgf2p8affineinvqb_, + vgf2p8affineqb_, vgf2p8mulb_, + vpshrd_, vpshld_, + vpshrdv_, vpshrdv__mask, vpshrdv__maskz, + vpshrdv__maskz_1, vpshldv_, vpshldv__mask, + vpshldv__maskz, vpshldv__maskz_1, vpdpbusd_, + vpdpbusd__mask, vpdpbusd__maskz, vpdpbusd__maskz_1, + vpdpbusds_, vpdpbusds__mask, vpdpbusds__maskz, + vpdpbusds__maskz_1, vpdpwssd_, vpdpwssd__mask, + vpdpwssd__maskz, vpdpwssd__maskz_1, vpdpwssds_, + vpdpwssds__mask, vpdpwssds__maskz, + vpdpwssds__maskz_1, vaesdec_, vaesdeclast_, + vaesenc_, vpclmulqdq_, + avx512vl_vpshufbitqmb): Formatting fixes. + 2017-12-28 Michael Meissner * builtins.def: (_Float and _FloatX BUILT_IN_CEIL): Add diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index f4f68eb5699..105b5cf6092 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -20082,10 +20082,11 @@ (define_insn "vgf2p8affineinvqb_" [(set (match_operand:VI1_AVX512F 0 "register_operand" "=x,x,v") - (unspec:VI1_AVX512F [(match_operand:VI1_AVX512F 1 "register_operand" "%0,x,v") - (match_operand:VI1_AVX512F 2 "nonimmediate_operand" "xBm,xm,vm") - (match_operand:QI 3 "const_0_to_255_operand" "n,n,n")] - UNSPEC_GF2P8AFFINEINV))] + (unspec:VI1_AVX512F + [(match_operand:VI1_AVX512F 1 "register_operand" "%0,x,v") + (match_operand:VI1_AVX512F 2 "nonimmediate_operand" "xBm,xm,vm") + (match_operand:QI 3 "const_0_to_255_operand" "n,n,n")] + UNSPEC_GF2P8AFFINEINV))] "TARGET_GFNI" "@ gf2p8affineinvqb\t{%3, %2, %0| %0, %2, %3} @@ -20099,10 +20100,11 @@ (define_insn "vgf2p8affineqb_" [(set (match_operand:VI1_AVX512F 0 "register_operand" "=x,x,v") - (unspec:VI1_AVX512F [(match_operand:VI1_AVX512F 1 "register_operand" "%0,x,v") - (match_operand:VI1_AVX512F 2 "nonimmediate_operand" "xBm,xm,vm") - (match_operand:QI 3 "const_0_to_255_operand" "n,n,n")] - UNSPEC_GF2P8AFFINE))] + (unspec:VI1_AVX512F + [(match_operand:VI1_AVX512F 1 "register_operand" "%0,x,v") + (match_operand:VI1_AVX512F 2 "nonimmediate_operand" "xBm,xm,vm") + (match_operand:QI 3 "const_0_to_255_operand" "n,n,n")] + UNSPEC_GF2P8AFFINE))] "TARGET_GFNI" "@ gf2p8affineqb\t{%3, %2, %0| %0, %2, %3} @@ -20116,9 +20118,10 @@ (define_insn "vgf2p8mulb_" [(set (match_operand:VI1_AVX512F 0 "register_operand" "=x,x,v") - (unspec:VI1_AVX512F [(match_operand:VI1_AVX512F 1 "register_operand" "%0,x,v") - (match_operand:VI1_AVX512F 2 "nonimmediate_operand" "xBm,xm,vm")] - UNSPEC_GF2P8MUL))] + (unspec:VI1_AVX512F + [(match_operand:VI1_AVX512F 1 "register_operand" "%0,x,v") + (match_operand:VI1_AVX512F 2 "nonimmediate_operand" "xBm,xm,vm")] + UNSPEC_GF2P8MUL))] "TARGET_GFNI" "@ gf2p8mulb\t{%2, %0| %0, %2} @@ -20134,9 +20137,9 @@ [(set (match_operand:VI248_VLBW 0 "register_operand" "=v") (unspec:VI248_VLBW [(match_operand:VI248_VLBW 1 "register_operand" "v") - (match_operand:VI248_VLBW 2 "nonimmediate_operand" "vm") - (match_operand:SI 3 "const_0_to_255_operand" "n") -] UNSPEC_VPSHRD))] + (match_operand:VI248_VLBW 2 "nonimmediate_operand" "vm") + (match_operand:SI 3 "const_0_to_255_operand" "n")] + UNSPEC_VPSHRD))] "TARGET_AVX512VBMI2" "vpshrd\t{%3, %2, %1, %0|%0, %1, %2, %3 }" [(set_attr ("prefix") ("evex"))]) @@ -20145,9 +20148,9 @@ [(set (match_operand:VI248_VLBW 0 "register_operand" "=v") (unspec:VI248_VLBW [(match_operand:VI248_VLBW 1 "register_operand" "v") - (match_operand:VI248_VLBW 2 "nonimmediate_operand" "vm") - (match_operand:SI 3 "const_0_to_255_operand" "n") -] UNSPEC_VPSHLD))] + (match_operand:VI248_VLBW 2 "nonimmediate_operand" "vm") + (match_operand:SI 3 "const_0_to_255_operand" "n")] + UNSPEC_VPSHLD))] "TARGET_AVX512VBMI2" "vpshld\t{%3, %2, %1, %0|%0, %1, %2, %3 }" [(set_attr ("prefix") ("evex"))]) @@ -20157,8 +20160,8 @@ (unspec:VI248_VLBW [(match_operand:VI248_VLBW 1 "register_operand" "0") (match_operand:VI248_VLBW 2 "register_operand" "v") - (match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm") -] UNSPEC_VPSHRDV))] + (match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm")] + UNSPEC_VPSHRDV))] "TARGET_AVX512VBMI2" "vpshrdv\t{%3, %2, %0|%0, %2, %3 }" [(set_attr ("prefix") ("evex")) @@ -20166,14 +20169,14 @@ (define_insn "vpshrdv__mask" [(set (match_operand:VI248_VLBW 0 "register_operand" "=v") - (vec_merge:VI248_VLBW (unspec:VI248_VLBW - [(match_operand:VI248_VLBW 1 "register_operand" "0") - (match_operand:VI248_VLBW 2 "register_operand" "v") - (match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm") - ] UNSPEC_VPSHRDV) - (match_dup 1) - (match_operand: 4 "register_operand" "Yk")) -)] + (vec_merge:VI248_VLBW + (unspec:VI248_VLBW + [(match_operand:VI248_VLBW 1 "register_operand" "0") + (match_operand:VI248_VLBW 2 "register_operand" "v") + (match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm")] + UNSPEC_VPSHRDV) + (match_dup 1) + (match_operand: 4 "register_operand" "Yk")))] "TARGET_AVX512VBMI2" "vpshrdv\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3 }" [(set_attr ("prefix") ("evex")) @@ -20187,22 +20190,23 @@ (match_operand: 4 "register_operand")] "TARGET_AVX512VBMI2" { - emit_insn (gen_vpshrdv__maskz_1 ( - operands[0], operands[1], operands[2], operands[3], - CONST0_RTX (mode), operands[4])); + emit_insn (gen_vpshrdv__maskz_1 (operands[0], operands[1], + operands[2], operands[3], + CONST0_RTX (mode), + operands[4])); DONE; }) (define_insn "vpshrdv__maskz_1" [(set (match_operand:VI248_VLBW 0 "register_operand" "=v") - (vec_merge:VI248_VLBW (unspec:VI248_VLBW - [(match_operand:VI248_VLBW 1 "register_operand" "0") - (match_operand:VI248_VLBW 2 "register_operand" "v") - (match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm") - ] UNSPEC_VPSHRDV) + (vec_merge:VI248_VLBW + (unspec:VI248_VLBW + [(match_operand:VI248_VLBW 1 "register_operand" "0") + (match_operand:VI248_VLBW 2 "register_operand" "v") + (match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm")] + UNSPEC_VPSHRDV) (match_operand:VI248_VLBW 4 "const0_operand" "C") - (match_operand: 5 "register_operand" "Yk")) -)] + (match_operand: 5 "register_operand" "Yk")))] "TARGET_AVX512VBMI2" "vpshrdv\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3 }" [(set_attr ("prefix") ("evex")) @@ -20213,8 +20217,8 @@ (unspec:VI248_VLBW [(match_operand:VI248_VLBW 1 "register_operand" "0") (match_operand:VI248_VLBW 2 "register_operand" "v") - (match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm") -] UNSPEC_VPSHLDV))] + (match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm")] + UNSPEC_VPSHLDV))] "TARGET_AVX512VBMI2" "vpshldv\t{%3, %2, %0|%0, %2, %3 }" [(set_attr ("prefix") ("evex")) @@ -20222,14 +20226,14 @@ (define_insn "vpshldv__mask" [(set (match_operand:VI248_VLBW 0 "register_operand" "=v") - (vec_merge:VI248_VLBW (unspec:VI248_VLBW - [(match_operand:VI248_VLBW 1 "register_operand" "0") - (match_operand:VI248_VLBW 2 "register_operand" "v") - (match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm") - ] UNSPEC_VPSHLDV) - (match_dup 1) - (match_operand: 4 "register_operand" "Yk")) -)] + (vec_merge:VI248_VLBW + (unspec:VI248_VLBW + [(match_operand:VI248_VLBW 1 "register_operand" "0") + (match_operand:VI248_VLBW 2 "register_operand" "v") + (match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm")] + UNSPEC_VPSHLDV) + (match_dup 1) + (match_operand: 4 "register_operand" "Yk")))] "TARGET_AVX512VBMI2" "vpshldv\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3 }" [(set_attr ("prefix") ("evex")) @@ -20243,22 +20247,23 @@ (match_operand: 4 "register_operand")] "TARGET_AVX512VBMI2" { - emit_insn (gen_vpshldv__maskz_1 ( - operands[0], operands[1], operands[2], operands[3], - CONST0_RTX (mode), operands[4])); + emit_insn (gen_vpshldv__maskz_1 (operands[0], operands[1], + operands[2], operands[3], + CONST0_RTX (mode), + operands[4])); DONE; }) (define_insn "vpshldv__maskz_1" [(set (match_operand:VI248_VLBW 0 "register_operand" "=v") - (vec_merge:VI248_VLBW (unspec:VI248_VLBW - [(match_operand:VI248_VLBW 1 "register_operand" "0") - (match_operand:VI248_VLBW 2 "register_operand" "v") - (match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm") - ] UNSPEC_VPSHLDV) + (vec_merge:VI248_VLBW + (unspec:VI248_VLBW + [(match_operand:VI248_VLBW 1 "register_operand" "0") + (match_operand:VI248_VLBW 2 "register_operand" "v") + (match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm")] + UNSPEC_VPSHLDV) (match_operand:VI248_VLBW 4 "const0_operand" "C") - (match_operand: 5 "register_operand" "Yk")) -)] + (match_operand: 5 "register_operand" "Yk")))] "TARGET_AVX512VBMI2" "vpshldv\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3 }" [(set_attr ("prefix") ("evex")) @@ -20269,22 +20274,22 @@ (unspec:VI4_AVX512VL [(match_operand:VI4_AVX512VL 1 "register_operand" "0") (match_operand:VI4_AVX512VL 2 "register_operand" "v") - (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm") -] UNSPEC_VPMADDUBSWACCD))] + (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")] + UNSPEC_VPMADDUBSWACCD))] "TARGET_AVX512VNNI" "vpdpbusd\t{%3, %2, %0|%0, %2, %3 }" [(set_attr ("prefix") ("evex"))]) (define_insn "vpdpbusd__mask" [(set (match_operand:VI4_AVX512VL 0 "register_operand" "=v") - (vec_merge:VI4_AVX512VL (unspec:VI4_AVX512VL - [(match_operand:VI4_AVX512VL 1 "register_operand" "0") - (match_operand:VI4_AVX512VL 2 "register_operand" "v") - (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm") - ] UNSPEC_VPMADDUBSWACCD) - (match_dup 1) - (match_operand: 4 "register_operand" "Yk")) -)] + (vec_merge:VI4_AVX512VL + (unspec:VI4_AVX512VL + [(match_operand:VI4_AVX512VL 1 "register_operand" "0") + (match_operand:VI4_AVX512VL 2 "register_operand" "v") + (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")] + UNSPEC_VPMADDUBSWACCD) + (match_dup 1) + (match_operand: 4 "register_operand" "Yk")))] "TARGET_AVX512VNNI" "vpdpbusd\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3 }" [(set_attr ("prefix") ("evex"))]) @@ -20297,22 +20302,23 @@ (match_operand: 4 "register_operand")] "TARGET_AVX512VNNI" { - emit_insn (gen_vpdpbusd__maskz_1 ( - operands[0], operands[1], operands[2], operands[3], - CONST0_RTX (mode), operands[4])); + emit_insn (gen_vpdpbusd__maskz_1 (operands[0], operands[1], + operands[2], operands[3], + CONST0_RTX (mode), + operands[4])); DONE; }) (define_insn "vpdpbusd__maskz_1" [(set (match_operand:VI4_AVX512VL 0 "register_operand" "=v") - (vec_merge:VI4_AVX512VL (unspec:VI4_AVX512VL - [(match_operand:VI4_AVX512VL 1 "register_operand" "0") - (match_operand:VI4_AVX512VL 2 "register_operand" "v") - (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm") - ] UNSPEC_VPMADDUBSWACCD) + (vec_merge:VI4_AVX512VL + (unspec:VI4_AVX512VL + [(match_operand:VI4_AVX512VL 1 "register_operand" "0") + (match_operand:VI4_AVX512VL 2 "register_operand" "v") + (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm") + ] UNSPEC_VPMADDUBSWACCD) (match_operand:VI4_AVX512VL 4 "const0_operand" "C") - (match_operand: 5 "register_operand" "Yk")) -)] + (match_operand: 5 "register_operand" "Yk")))] "TARGET_AVX512VNNI" "vpdpbusd\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3 }" [(set_attr ("prefix") ("evex"))]) @@ -20323,22 +20329,22 @@ (unspec:VI4_AVX512VL [(match_operand:VI4_AVX512VL 1 "register_operand" "0") (match_operand:VI4_AVX512VL 2 "register_operand" "v") - (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm") -] UNSPEC_VPMADDUBSWACCSSD))] + (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")] + UNSPEC_VPMADDUBSWACCSSD))] "TARGET_AVX512VNNI" "vpdpbusds\t{%3, %2, %0|%0, %2, %3 }" [(set_attr ("prefix") ("evex"))]) (define_insn "vpdpbusds__mask" [(set (match_operand:VI4_AVX512VL 0 "register_operand" "=v") - (vec_merge:VI4_AVX512VL (unspec:VI4_AVX512VL - [(match_operand:VI4_AVX512VL 1 "register_operand" "0") - (match_operand:VI4_AVX512VL 2 "register_operand" "v") - (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm") - ] UNSPEC_VPMADDUBSWACCSSD) - (match_dup 1) - (match_operand: 4 "register_operand" "Yk")) -)] + (vec_merge:VI4_AVX512VL + (unspec:VI4_AVX512VL + [(match_operand:VI4_AVX512VL 1 "register_operand" "0") + (match_operand:VI4_AVX512VL 2 "register_operand" "v") + (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")] + UNSPEC_VPMADDUBSWACCSSD) + (match_dup 1) + (match_operand: 4 "register_operand" "Yk")))] "TARGET_AVX512VNNI" "vpdpbusds\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3 }" [(set_attr ("prefix") ("evex"))]) @@ -20351,22 +20357,23 @@ (match_operand: 4 "register_operand")] "TARGET_AVX512VNNI" { - emit_insn (gen_vpdpbusds__maskz_1 ( - operands[0], operands[1], operands[2], operands[3], - CONST0_RTX (mode), operands[4])); + emit_insn (gen_vpdpbusds__maskz_1 (operands[0], operands[1], + operands[2], operands[3], + CONST0_RTX (mode), + operands[4])); DONE; }) (define_insn "vpdpbusds__maskz_1" [(set (match_operand:VI4_AVX512VL 0 "register_operand" "=v") - (vec_merge:VI4_AVX512VL (unspec:VI4_AVX512VL - [(match_operand:VI4_AVX512VL 1 "register_operand" "0") - (match_operand:VI4_AVX512VL 2 "register_operand" "v") - (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm") - ] UNSPEC_VPMADDUBSWACCSSD) + (vec_merge:VI4_AVX512VL + (unspec:VI4_AVX512VL + [(match_operand:VI4_AVX512VL 1 "register_operand" "0") + (match_operand:VI4_AVX512VL 2 "register_operand" "v") + (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")] + UNSPEC_VPMADDUBSWACCSSD) (match_operand:VI4_AVX512VL 4 "const0_operand" "C") - (match_operand: 5 "register_operand" "Yk")) -)] + (match_operand: 5 "register_operand" "Yk")))] "TARGET_AVX512VNNI" "vpdpbusds\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3 }" [(set_attr ("prefix") ("evex"))]) @@ -20377,22 +20384,22 @@ (unspec:VI4_AVX512VL [(match_operand:VI4_AVX512VL 1 "register_operand" "0") (match_operand:VI4_AVX512VL 2 "register_operand" "v") - (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm") -] UNSPEC_VPMADDWDACCD))] + (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")] + UNSPEC_VPMADDWDACCD))] "TARGET_AVX512VNNI" "vpdpwssd\t{%3, %2, %0|%0, %2, %3 }" [(set_attr ("prefix") ("evex"))]) (define_insn "vpdpwssd__mask" [(set (match_operand:VI4_AVX512VL 0 "register_operand" "=v") - (vec_merge:VI4_AVX512VL (unspec:VI4_AVX512VL - [(match_operand:VI4_AVX512VL 1 "register_operand" "0") - (match_operand:VI4_AVX512VL 2 "register_operand" "v") - (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm") - ] UNSPEC_VPMADDWDACCD) - (match_dup 1) - (match_operand: 4 "register_operand" "Yk")) -)] + (vec_merge:VI4_AVX512VL + (unspec:VI4_AVX512VL + [(match_operand:VI4_AVX512VL 1 "register_operand" "0") + (match_operand:VI4_AVX512VL 2 "register_operand" "v") + (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")] + UNSPEC_VPMADDWDACCD) + (match_dup 1) + (match_operand: 4 "register_operand" "Yk")))] "TARGET_AVX512VNNI" "vpdpwssd\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3 }" [(set_attr ("prefix") ("evex"))]) @@ -20405,22 +20412,23 @@ (match_operand: 4 "register_operand")] "TARGET_AVX512VNNI" { - emit_insn (gen_vpdpwssd__maskz_1 ( - operands[0], operands[1], operands[2], operands[3], - CONST0_RTX (mode), operands[4])); + emit_insn (gen_vpdpwssd__maskz_1 (operands[0], operands[1], + operands[2], operands[3], + CONST0_RTX (mode), + operands[4])); DONE; }) (define_insn "vpdpwssd__maskz_1" [(set (match_operand:VI4_AVX512VL 0 "register_operand" "=v") - (vec_merge:VI4_AVX512VL (unspec:VI4_AVX512VL - [(match_operand:VI4_AVX512VL 1 "register_operand" "0") - (match_operand:VI4_AVX512VL 2 "register_operand" "v") - (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm") - ] UNSPEC_VPMADDWDACCD) + (vec_merge:VI4_AVX512VL + (unspec:VI4_AVX512VL + [(match_operand:VI4_AVX512VL 1 "register_operand" "0") + (match_operand:VI4_AVX512VL 2 "register_operand" "v") + (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")] + UNSPEC_VPMADDWDACCD) (match_operand:VI4_AVX512VL 4 "const0_operand" "C") - (match_operand: 5 "register_operand" "Yk")) -)] + (match_operand: 5 "register_operand" "Yk")))] "TARGET_AVX512VNNI" "vpdpwssd\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3 }" [(set_attr ("prefix") ("evex"))]) @@ -20431,22 +20439,22 @@ (unspec:VI4_AVX512VL [(match_operand:VI4_AVX512VL 1 "register_operand" "0") (match_operand:VI4_AVX512VL 2 "register_operand" "v") - (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm") -] UNSPEC_VPMADDWDACCSSD))] + (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")] + UNSPEC_VPMADDWDACCSSD))] "TARGET_AVX512VNNI" "vpdpwssds\t{%3, %2, %0|%0, %2, %3 }" [(set_attr ("prefix") ("evex"))]) (define_insn "vpdpwssds__mask" [(set (match_operand:VI4_AVX512VL 0 "register_operand" "=v") - (vec_merge:VI4_AVX512VL (unspec:VI4_AVX512VL - [(match_operand:VI4_AVX512VL 1 "register_operand" "0") - (match_operand:VI4_AVX512VL 2 "register_operand" "v") - (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm") - ] UNSPEC_VPMADDWDACCSSD) - (match_dup 1) - (match_operand: 4 "register_operand" "Yk")) -)] + (vec_merge:VI4_AVX512VL + (unspec:VI4_AVX512VL + [(match_operand:VI4_AVX512VL 1 "register_operand" "0") + (match_operand:VI4_AVX512VL 2 "register_operand" "v") + (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")] + UNSPEC_VPMADDWDACCSSD) + (match_dup 1) + (match_operand: 4 "register_operand" "Yk")))] "TARGET_AVX512VNNI" "vpdpwssds\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3 }" [(set_attr ("prefix") ("evex"))]) @@ -20459,29 +20467,30 @@ (match_operand: 4 "register_operand")] "TARGET_AVX512VNNI" { - emit_insn (gen_vpdpwssds__maskz_1 ( - operands[0], operands[1], operands[2], operands[3], - CONST0_RTX (mode), operands[4])); + emit_insn (gen_vpdpwssds__maskz_1 (operands[0], operands[1], + operands[2], operands[3], + CONST0_RTX (mode), + operands[4])); DONE; }) (define_insn "vpdpwssds__maskz_1" [(set (match_operand:VI4_AVX512VL 0 "register_operand" "=v") - (vec_merge:VI4_AVX512VL (unspec:VI4_AVX512VL - [(match_operand:VI4_AVX512VL 1 "register_operand" "0") - (match_operand:VI4_AVX512VL 2 "register_operand" "v") - (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm") - ] UNSPEC_VPMADDWDACCSSD) + (vec_merge:VI4_AVX512VL + (unspec:VI4_AVX512VL + [(match_operand:VI4_AVX512VL 1 "register_operand" "0") + (match_operand:VI4_AVX512VL 2 "register_operand" "v") + (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")] + UNSPEC_VPMADDWDACCSSD) (match_operand:VI4_AVX512VL 4 "const0_operand" "C") - (match_operand: 5 "register_operand" "Yk")) -)] + (match_operand: 5 "register_operand" "Yk")))] "TARGET_AVX512VNNI" "vpdpwssds\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3 }" [(set_attr ("prefix") ("evex"))]) (define_insn "vaesdec_" [(set (match_operand:VI1_AVX512VL_F 0 "register_operand" "=v") - (unspec:VI1_AVX512VL_F + (unspec:VI1_AVX512VL_F [(match_operand:VI1_AVX512VL_F 1 "register_operand" "v") (match_operand:VI1_AVX512VL_F 2 "vector_operand" "v")] UNSPEC_VAESDEC))] @@ -20491,7 +20500,7 @@ (define_insn "vaesdeclast_" [(set (match_operand:VI1_AVX512VL_F 0 "register_operand" "=v") - (unspec:VI1_AVX512VL_F + (unspec:VI1_AVX512VL_F [(match_operand:VI1_AVX512VL_F 1 "register_operand" "v") (match_operand:VI1_AVX512VL_F 2 "vector_operand" "v")] UNSPEC_VAESDECLAST))] @@ -20501,7 +20510,7 @@ (define_insn "vaesenc_" [(set (match_operand:VI1_AVX512VL_F 0 "register_operand" "=v") - (unspec:VI1_AVX512VL_F + (unspec:VI1_AVX512VL_F [(match_operand:VI1_AVX512VL_F 1 "register_operand" "v") (match_operand:VI1_AVX512VL_F 2 "vector_operand" "vm")] UNSPEC_VAESENC))] @@ -20511,7 +20520,7 @@ (define_insn "vaesenclast_" [(set (match_operand:VI1_AVX512VL_F 0 "register_operand" "=v") - (unspec:VI1_AVX512VL_F + (unspec:VI1_AVX512VL_F [(match_operand:VI1_AVX512VL_F 1 "register_operand" "v") (match_operand:VI1_AVX512VL_F 2 "vector_operand" "vm")] UNSPEC_VAESENCLAST))] @@ -20522,9 +20531,9 @@ (define_insn "vpclmulqdq_" [(set (match_operand:VI8_FVL 0 "register_operand" "=v") (unspec:VI8_FVL [(match_operand:VI8_FVL 1 "register_operand" "v") - (match_operand:VI8_FVL 2 "vector_operand" "vm") - (match_operand:SI 3 "const_0_to_255_operand" "n")] - UNSPEC_VPCLMULQDQ))] + (match_operand:VI8_FVL 2 "vector_operand" "vm") + (match_operand:SI 3 "const_0_to_255_operand" "n")] + UNSPEC_VPCLMULQDQ))] "TARGET_VPCLMULQDQ" "vpclmulqdq\t{%3, %2, %1, %0|%0, %1, %2, %3}" [(set_attr "mode" "DI")]) @@ -20534,7 +20543,7 @@ (unspec: [(match_operand:VI48_AVX512VLBW 1 "register_operand" "v") (match_operand:VI48_AVX512VLBW 2 "nonimmediate_operand" "vm")] - UNSPEC_VPSHUFBIT))] + UNSPEC_VPSHUFBIT))] "TARGET_AVX512BITALG" "vpshufbitqmb\t{%2, %1, %0|%0, %1, %2}" [(set_attr "prefix" "evex")