From: bugzilla-daemon <bugzilla-daemon@libre-soc.org>
Date: Mon, 8 Jun 2020 22:03:38 +0000 (+0000)
Subject: [libre-riscv-dev] [Bug 370] need a way to co-simulate hardware, qemu, microwatt,... 
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1e4ba9ae44ca556bcbc51cbb6e3618f87665fdc7;p=libre-riscv-dev.git

[libre-riscv-dev] [Bug 370] need a way to co-simulate hardware, qemu, microwatt, simulator, side-by-side
---

diff --git a/14/72438f0aaba8d88f8ba0e2e9f77967c8b27d9e b/14/72438f0aaba8d88f8ba0e2e9f77967c8b27d9e
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+Date: Mon, 08 Jun 2020 22:03:38 +0000
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+X-Bugzilla-Component: Source Code
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+X-Bugzilla-Severity: enhancement
+X-Bugzilla-Who: lkcl@lkcl.net
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+Subject: [libre-riscv-dev] [Bug 370] need a way to co-simulate hardware, qemu,
+ microwatt, simulator, side-by-side
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+
+aHR0cHM6Ly9idWdzLmxpYnJlLXNvYy5vcmcvc2hvd19idWcuY2dpP2lkPTM3MAoKLS0tIENvbW1l
+bnQgIzIgZnJvbSBMdWtlIEtlbm5ldGggQ2Fzc29uIExlaWdodG9uIDxsa2NsQGxrY2wubmV0PiAt
+LS0KKEluIHJlcGx5IHRvIE1pY2hhZWwgTm9sYW4gZnJvbSBjb21tZW50ICMxKQo+IEN5Y2xlIGFj
+Y3VyYXRlIC0gYXMgaW4gY2hlY2tpbmcgdGhhdCB0aGUgcmVzdWx0cyBhcmUgdGhlIHNhbWUgYWZ0
+ZXIgZXZlcnkKPiBzdGVwPwoKY3ljbGUtYWNjdXJhdGUgbWVhbnMgdGhhdCB5ZXMsIHlvdSBfY291
+bGRfIGNoZWNrIHRoYXQgdGhlIHJlc3VsdHMgYXJlIHRoZQpzYW1lIGFmdGVyIGV2ZXJ5IHN0ZXAg
+dGhyb3VnaCBlYWNoIGFuZCBldmVyeSBpbnN0cnVjdGlvbiAobm90IHRoYXQgeW91CmFic29sdXRl
+bHkKaGF2ZSB0bzogaXQncyBqdXN0IHRoYXQgaXQncyBwb3NzaWJsZSB0byBkbyBzbykuCgphIEpJ
+VCBjb21waWxlciAocGVhcnBjJ3MgSklULCBxZW11IEpJVCkgdGhhdCBpcyB2ZXJ5IHNwZWNpZmlj
+YWxseSAqbm90KgpndWFyYW50ZWVkIHRvIGJlIHRoZSBjYXNlLCBiZWNhdXNlIHNldmVyYWwgZW11
+bGF0ZWQgaW5zdHJ1Y3Rpb25zIGNhbiBlbmQgdXAKYmVpbmcKcmVwbGFjZWQgYnkgb25lIChvcHRp
+bWlzZWQpIHNlcXVlbmNlIG9mIGhvc3QtbmF0aXZlIGluc3RydWN0aW9ucy4KCkpJVC10cmFuc2xh
+dGVkIGNvZGUgd291bGQgY2xlYXJseSBiZSBhYnNvbHV0ZWx5IHVzZWxlc3MgZm9yIHVzIHRvIGF0
+dGVtcHQgdG8KcnVuIGFuZCBjb21wYXJlIGFnYWluc3QsIGZvciB0aGF0IHJlYXNvbi4KCnNwaWtl
+ICh0aGUgUklTQy1WIHNpbXVsYXRvcikgd2VudCB0byBhIGxvdCBvZiB0cm91YmxlIHRvIGV2ZW4g
+bWFpbnRhaW4KY3ljbGUtYWNjdXJhdGUgZW11bGF0aW9uIG9mIHRoZSBQVFcsIHRoZSBNTVUgLSBw
+cmV0dHkgbXVjaCBldmVyeXRoaW5nLAoqc3BlY2lmaWNhbGx5KiBzbyB0aGF0IHRoZSBzb2Z0d2Fy
+ZSAoQkJMLCBsaW51eCBrZXJuZWwgZXRjLikgY291bGQgYmUgd29ya2VkIG9uCmluIHBhcmFsbGVs
+IHdpdGggZGV2ZWxvcG1lbnQgb2Ygc29tZSBoYXJkd2FyZSwgYW5kIHRoZSBzcGVjaWZpY2F0aW9u
+IGZvcm1hbGlzZWQKZXZlbiBiZWZvcmUgdGhhdC4KCi0tIApZb3UgYXJlIHJlY2VpdmluZyB0aGlz
+IG1haWwgYmVjYXVzZToKWW91IGFyZSBvbiB0aGUgQ0MgbGlzdCBmb3IgdGhlIGJ1Zy4KX19fX19f
+X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KbGlicmUtcmlzY3YtZGV2
+IG1haWxpbmcgbGlzdApsaWJyZS1yaXNjdi1kZXZAbGlzdHMubGlicmUtcmlzY3Yub3JnCmh0dHA6
+Ly9saXN0cy5saWJyZS1yaXNjdi5vcmcvbWFpbG1hbi9saXN0aW5mby9saWJyZS1yaXNjdi1kZXYK
+