From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 3 May 2019 21:03:51 +0000 (-0700)
Subject: iverilog with simcells.v as well
X-Git-Tag: yosys-0.9~154
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1e5f072c0556158924387dedbb78b4cc61bfcf7a;p=yosys.git

iverilog with simcells.v as well
---

diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh
index bb9c3bfb5..920474a84 100755
--- a/tests/tools/autotest.sh
+++ b/tests/tools/autotest.sh
@@ -147,7 +147,8 @@ do
 		fi
 		if $genvcd; then sed -i 's,// \$dump,$dump,g' ${bn}_tb.v; fi
 		compile_and_run ${bn}_tb_ref ${bn}_out_ref ${bn}_tb.v ${bn}_ref.v $libs \
-					"$toolsdir"/../../techlibs/common/simlib.v
+					"$toolsdir"/../../techlibs/common/simlib.v \
+					"$toolsdir"/../../techlibs/common/simcells.v
 		if $genvcd; then mv testbench.vcd ${bn}_ref.vcd; fi
 
 		test_count=0