From: Tobias Platen Date: Fri, 21 Aug 2020 18:49:14 +0000 (+0200) Subject: typo fix in test_l0_cache_buffer2.py X-Git-Tag: semi_working_ecp5~272^2~40 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1e651d83571fc0dee9f454188d4d34b3c708789e;p=soc.git typo fix in test_l0_cache_buffer2.py --- diff --git a/src/soc/experiment/test/test_l0_cache_buffer2.py b/src/soc/experiment/test/test_l0_cache_buffer2.py index ba2a8170..f23536e9 100644 --- a/src/soc/experiment/test/test_l0_cache_buffer2.py +++ b/src/soc/experiment/test/test_l0_cache_buffer2.py @@ -35,7 +35,7 @@ class TestCachedMemoryPortInterface(PortInterfaceBase): #m.d.comb += self..eq(msbaddr) def set_wr_data(self, m, data, wen): - m.d.comb += self.ldst.st_data_i.eq(data) # write st to mem + m.d.comb += self.ldst.st_data_i.data.eq(data) # write st to mem m.d.comb += self.ldst.is_st_i.eq(wen) # enable writes return Const(1, 1) #fixme -- write may be longer than one cycle