From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Sun, 1 Mar 2015 15:52:50 +0000 (+0100)
Subject: uart: add sim phy
X-Git-Tag: 24jan2021_ls180~2546
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1e6d1deae83a5f80f611645c2f72facd50f34b37;p=litex.git

uart: add sim phy
---

diff --git a/misoclib/com/uart/phy/sim.py b/misoclib/com/uart/phy/sim.py
new file mode 100644
index 00000000..177b97ca
--- /dev/null
+++ b/misoclib/com/uart/phy/sim.py
@@ -0,0 +1,18 @@
+from migen.fhdl.std import *
+from migen.flow.actor import Sink, Source
+
+class UARTPHYSim(Module):
+	def __init__(self, pads):
+		self.dw = 8
+		self.tuning_word = Signal(32)
+		self.sink = Sink([("d", 8)])
+		self.source = Source([("d", 8)])
+
+		self.comb += [
+			pads.source_stb.eq(self.sink.stb),
+			pads.source_d.eq(self.sink.d),
+			self.sink.ack.eq(pads.source_ack),
+
+			self.source.stb.eq(pads.sink_stb),
+			self.source.d.eq(pads.sink_d)
+		]