From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 17 Jan 2020 19:14:19 +0000 (-0800)
Subject: +/xilinx/arith_map.v fix $lcu rule
X-Git-Tag: working-ls180~861^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1e6d56dca11c7a632b74ba51361f879dc706110a;p=yosys.git

+/xilinx/arith_map.v fix $lcu rule
---

diff --git a/techlibs/xilinx/arith_map.v b/techlibs/xilinx/arith_map.v
index 5c848d4e6..c345a3da3 100644
--- a/techlibs/xilinx/arith_map.v
+++ b/techlibs/xilinx/arith_map.v
@@ -53,9 +53,9 @@ module _80_xilinx_lcu (P, G, CI, CO);
 				(
 				.CYINIT(CI),
 				.CI    (1'd0),
-				.DI    (G [(Y_WIDTH - 1):i*4]),
-				.S     (S [(Y_WIDTH - 1):i*4]),
-				.CO    (CO[(Y_WIDTH - 1):i*4]),
+				.DI    (G [(WIDTH - 1):i*4]),
+				.S     (S [(WIDTH - 1):i*4]),
+				.CO    (CO[(WIDTH - 1):i*4]),
 				);
 			// Another one
 			end else begin
@@ -63,9 +63,9 @@ module _80_xilinx_lcu (P, G, CI, CO);
 				(
 				.CYINIT(1'd0),
 				.CI    (C [i*4 - 1]),
-				.DI    (G [(Y_WIDTH - 1):i*4]),
-				.S     (S [(Y_WIDTH - 1):i*4]),
-				.CO    (CO[(Y_WIDTH - 1):i*4]),
+				.DI    (G [(WIDTH - 1):i*4]),
+				.S     (S [(WIDTH - 1):i*4]),
+				.CO    (CO[(WIDTH - 1):i*4]),
 				);
 			end