From: lkcl <lkcl@web>
Date: Sat, 15 May 2021 17:11:47 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~913
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1e6f95fa594569e8cbfcb2f620f3a2cdf787bf52;p=libreriscv.git

---

diff --git a/openpower.mdwn b/openpower.mdwn
index 614b9c31b..4506c9653 100644
--- a/openpower.mdwn
+++ b/openpower.mdwn
@@ -10,10 +10,10 @@ Libre-SOC is basing its [[Simple-V Vectorisation|sv]] CPU extensions on OpenPOWE
 is designed for high performance.
 
 See wikipedia page 
-https://en.m.wikipedia.org/wiki/Power_ISA
+<https://en.m.wikipedia.org/wiki/Power_ISA>
 
 very useful resource describing all assembly instructions
-https://www.ibm.com/docs/en/aix/7.1?topic=reference-instruction-set
+<https://www.ibm.com/docs/en/aix/7.1?topic=reference-instruction-set>
 
 # Evaluation